[PATCH] arm64: errata: Add NXP iMX8QM workaround for A53 Cache coherency issue

[Robin Murphy]

On 2023-04-13 12:19, Mark Rutland wrote:
[...]
>> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
>> index 6bf013fb110d..1ed648f7f29a 100644
>> --- a/arch/arm64/include/asm/cpufeature.h
>> +++ b/arch/arm64/include/asm/cpufeature.h
>> @@ -835,7 +835,8 @@ static inline bool system_supports_bti(void)
>>   static inline bool system_supports_tlb_range(void)
>>   {
>>   	return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
>> -		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
>> +		cpus_have_const_cap(ARM64_HAS_TLB_RANGE) &&
>> +		!cpus_have_const_cap(ARM64_WORKAROUND_NXP_ERR050104);
>>   }
> 
> It'd be better to handle this in the detection of ARM64_HAS_TLB_RANGE, as we
> have for CNP where has_useable_cnp() checks for ARM64_WORKAROUND_NVIDIA_CARMEL_CNP.

It's not needed in either place, since neither Cortex-A53 or Cortex-A72 
support FEAT_TLBIRANGE, so this could never be true on affected 
platforms anyway.

Tangentially, I understand this platform has an SMMU[1], so I'd say it 
would also be worth checking what SMMU_IDR0.BTM reports. With any luck 
it might be 0, but if it's 1 then strictly it would want to be 
overridden as part of a complete workaround as well. That wouldn't be a 
practical issue right now, not least since the current Linux driver 
doesn't even use BTM, but it's something which could need to be borne in 
mind in future.

Robin.

[1] 
https://lore.kernel.org/linux-arm-kernel/20210807104517.24066-1-peng.fan@oss.nxp.com/