[PATCH 1/2] KVM: arm64: nvhe: Synchronise with page table walker on MMU update

[Marc Zyngier]

Hi Oliver,

On Thu, 06 Apr 2023 17:56:31 +0100,
Oliver Upton <oliver.upton at linux.dev> wrote:
> 
> Hey Marc,
> 
> On Thu, Mar 30, 2023 at 11:04:18AM +0100, Marc Zyngier wrote:
> > When taking an exception between the EL1&0 translation regime and
> > the EL2 translation regime, the page table walker is allowed to
> > complete the walks started from EL0 or EL1 while running at EL2.
> > 
> > It means that altering the system registers that define the EL1&0
> > translation regime is fraught with danger *unless* we wait for
> > the completion of such walk with a DSB (R_LFHQG and subsequent
> > statements in the ARM ARM). We already did the right thing for
> > other external agents (SPE, TRBE), but not the PTW.
> > 
> > In the case of nVHE, this is a bit involved, as there are a number
> > of situations where this can happen (such as switching between
> > host and guest, invalidating TLBs...).
> 
> I'm assuming that the dsb(ishst) done in some of the other TLB
> invalidation handlers is sufficient, as R_LFHQG does not describe the
> scope of the DSB (i.e. loads and/or stores). Nonetheless, short of any
> special serialization rules, it seems probable for the PTW to have both
> outstanding loads and stores.

I too find the definition pretty light. My gut feeling is that we're
not really trying to synchronise against either loads or stores. We
are simply waiting for the PTW to complete (or give up) potential
speculative walks.

For TLBIs, we want to make sure that prior writes to the PTs are
observable, specially as we perform a broadcast invalidation.

But for external agents, we seem to always rely on an dsb(nsh), such
as for TRBE and SPE. My take is that if it is enough for them, it
should be enough for the PTW.

> Is there some other language in the architecture that speaks to the
> effects of _any_ DSB on the PTW? I couldn't find it myself. In any case,
> I'll have to take you at your word if you say it is sufficient :)

"Data Synchronization Barrier (DSB)" has a tiny bit more info, but
that's really thin.

Maybe some of the ARM folks on cc can chime in?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.