[PATCH v2 2/2] arm64: dts: realtek: Add RTD1319 SoC and Realtek Pym Particles EVB
Krzysztof Kozlowski
krzysztof.kozlowski at linaro.org
Thu Apr 6 10:20:38 PDT 2023
On 06/04/2023 09:18, CY_Huang[黃鉦晏] wrote:
> Add Device Trees for Realtek RTD1319 SoC family, RTD1319 SoC and
> Realtek Pym Particles EVB.
>
> Signed-off-by: cy.huang <cy.huang at realtek.com>
> ---
> v1->v2:
> * no change
> v1:
> * RTD1319 SoC and Realtek PymParticle EVB
>
> arch/arm64/boot/dts/realtek/Makefile | 2 +
> .../boot/dts/realtek/rtd1319-pymparticles.dts | 28 ++
> arch/arm64/boot/dts/realtek/rtd13xx.dtsi | 346 ++++++++++++++++++
> 3 files changed, 376 insertions(+)
> create mode 100644 arch/arm64/boot/dts/realtek/rtd1319-pymparticles.dts
> create mode 100644 arch/arm64/boot/dts/realtek/rtd13xx.dtsi
>
> diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile
> index ef8d8fcbaa05..ef569b8ebd13 100644
> --- a/arch/arm64/boot/dts/realtek/Makefile
> +++ b/arch/arm64/boot/dts/realtek/Makefile
> @@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
> dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
>
> dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
> +
> +dtb-$(CONFIG_ARCH_REALTEK) += rtd1319-pymparticles.dtb
> diff --git a/arch/arm64/boot/dts/realtek/rtd1319-pymparticles.dts b/arch/arm64/boot/dts/realtek/rtd1319-pymparticles.dts
> new file mode 100644
> index 000000000000..6e46bf9ac252
> --- /dev/null
> +++ b/arch/arm64/boot/dts/realtek/rtd1319-pymparticles.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-3.0-or-later OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2019-2020 Realtek Semiconductor Corp.
> + */
> +
> +/dts-v1/;
> +
> +#include "rtd13xx.dtsi"
> +
> +/ {
> + compatible = "realtek,pym-particles", "realtek,rtd1319";
> + model = "Realtek Pym Particles EVB";
> +
> + memory at 40000 {
> + device_type = "memory";
> + reg = <0x00040000 0x7ffc0000>; /* boot ROM to 1 GiB or 2 GiB */
> + };
> +
> + chosen {
> + stdout-path = "serial0:460800n8";
> + };
> +};
> +
> +/* debug console (J1) */
> +&uart0 {
> + status = "okay";
> +};
> +
Drop stray blank lines. Same in second file.
> diff --git a/arch/arm64/boot/dts/realtek/rtd13xx.dtsi b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi
> new file mode 100644
> index 000000000000..59af2489e170
> --- /dev/null
> +++ b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi
> @@ -0,0 +1,346 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
> +/*
> + * Realtek RTD13xx SoC family
> + *
> + * Copyright (c) 2019-2020 Realtek Semiconductor Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + protected_mem: protected_mem at 40000 {
No underscores in node names.
> + reg = <0x00040000 0x1000000>;
> + no-map;
> + };
> +
> + rpc_comm: comm at 4080000 {
> + reg = <0x04080000 0x1000>;
> + };
> +
> + rpc_ringbuf: ringbuf at 40ff000 {
> + reg = <0x040ff000 0x4000>;
> + };
> +
> + audio_heap: audio_heap at 4200000 {
> + reg = <0x04200000 0xc00000>;
> + };
> +
> + media_heap: media_heap at 4e00000 {
> + reg = <0x04e00000 0x06000000>;
> + };
> +
> + audio_fw_mem: audio_fw_mem at 10000000 {
> + reg = <0x10000000 0x14000>;
> + no-map;
> + };
> +
> + tee: tee at 10100000 {
> + reg = <0x10100000 0x04100000>;
> + no-map;
> + };
> +
> + cma_resrved_0:linux,default_cma {
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + compatible = "shared-dma-pool";
> + size = <0x02000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x80000000>;
> + linux,cma-default;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_1:linux,cma_1 {
> + compatible = "shared-dma-pool";
> + size = <0x02000000>;
> + alloc-ranges=<0x14200000 0x0be00000>;
> + linux,contiguous-region;
> + reusable;
> + status = "disabled";
> + };
> +
> + cma_resrved_2:linux,cma_2 {
> + compatible = "shared-dma-pool";
> + size = <0x08000000>;
> + alloc-ranges=<0x00000000 0x60000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_3:linux,cma_3 {
> + compatible = "shared-dma-pool";
> + size = <0x10000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x80000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_4:linux,cma_4 {
> + compatible = "shared-dma-pool";
> + size = <0x02000000>;
> + alignment = <0x01000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_5:linux,cma_5 {
> + compatible = "shared-dma-pool";
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x60000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_6:linux,cma_6 {
> + compatible = "shared-dma-pool";
> + size = <0x02000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x60000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_7:linux,cma_7 {
> + compatible = "shared-dma-pool";
> + size = <0x01000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x60000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_8:linux,cma_8 {
> + compatible = "shared-dma-pool";
> + size = <0x06000000>;
> + alignment = <0x01000000>;
> + alloc-ranges=<0x00000000 0x60000000>;
> + linux,contiguous-region;
> + reusable;
> + };
> +
> + cma_resrved_9:linux,cma_9 {
> + compatible = "shared-dma-pool";
> + reusable;
> + size = <0x04000000>;
> + alignment = <0x01000000>;
> + linux,contiguous-region;
> + alloc-ranges=<0x00000000 0x60000000>;
> + };
> + };
> +
> + clocks {
> + osc27m: osc {
Use consistent naming. If other is "-clk" this should be as well.
> + compatible = "fixed-clock";
> + clock-frequency = <27000000>;
Isn't this located on the board? Physically on the board?
> + clock-output-names = "osc27m";
> + #clock-cells = <0>;
> + };
> +
> + baudclk: baudclk {
baud-clk
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <432000000>;
> + clock-output-names = "baudclk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x100>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu2: cpu at 200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x200>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu3: cpu at 300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x300>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + arm_pmu: pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + soc at 0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
> + <0x00030000 0x00030000 0x00030000>, /* PCIE IO*/
> + <0xff100000 0xff100000 0x00200000>, /* GIC */
> + <0xC0000000 0xC0000000 0x00100000>,
> + <0xC1000000 0xC1000000 0x00100000>,
> + <0x98000000 0x98000000 0x00200000>; /* rbus */
> +
> + rbus: rbus at 98000000 {
> + compatible = "simple-bus";
> + reg = <0x98000000 0x200000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x98000000 0x200000>,
> + <0xC0000000 0xC0000000 0x00100000>,
> + <0xC1000000 0xC1000000 0x00100000>,
> + <0x10030000 0x00030000 0x00030000>; /* PCIE IO*/
> +
> + crt: syscon at 0 {
> + compatible = "syscon", "simple-mfd";
These are not allowed on their own. Your patchset is really not tested
against bindings.
> + reg = <0x0 0x1000>;
> + reg-io-width = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x1000>;
> + };
> +
> + pinctrl: pinctrl at 4e000 {
> + compatible = "syscon";
syscon as pinctrl? Nope.
> + reg = <0x4e000 0x130>;
> + reg-io-width = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
??
> + #gpio-range-cells = <3>;
> + ranges = <0x0 0x4e000 0x130>;
> + };
> +
> + iso: syscon at 7000 {
> + compatible = "syscon", "simple-mfd";
NAK
> + reg = <0x7000 0x1000>;
> + reg-io-width = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
NAK even more, you do not have children.
> + ranges = <0x0 0x7000 0x1000>;
> + };
> +
> + sb2: syscon at 1a000 {
> + compatible = "syscon", "simple-mfd";
So your entire SoC is just bunch of syscons and interrupt controller.
That's not suitable for upstream at all. Define a real hardware and a
real DTS.
Best regards,
Krzysztof
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