[PATCH] arm64: dts: imx8mm: Add display pipeline components

[Alexander Stein]

Hi Marek,

Am Dienstag, 4. April 2023, 02:01:51 CEST schrieb Marek Vasut:
> Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini.
> This makes the DSI display pipeline available on this SoC.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: Abel Vesa <abel.vesa at nxp.com>
> Cc: Dong Aisheng <aisheng.dong at nxp.com>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Guido Günther <agx at sigxcpu.org>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
> Cc: Richard Cochran <richardcochran at gmail.com>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index
> e311da7e87bdc..06495c225c94b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1119,6 +1119,63 @@ aips4: bus at 32c00000 {
>  			#size-cells = <1>;
>  			ranges = <0x32c00000 0x32c00000 0x400000>;
> 
> +			lcdif: lcdif at 32e00000 {
> +				compatible = "fsl,imx8mm-lcdif", 
"fsl,imx6sx-lcdif";
> +				reg = <0x32e00000 0x10000>;
> +				clocks = <&clk 
IMX8MM_CLK_LCDIF_PIXEL>,
> +					 <&clk 
IMX8MM_CLK_DISP_APB_ROOT>,
> +					 <&clk 
IMX8MM_CLK_DISP_AXI_ROOT>;
> +				clock-names = "pix", "axi", 
"disp_axi";
> +				assigned-clocks = <&clk 
IMX8MM_CLK_LCDIF_PIXEL>,
> +						  <&clk 
IMX8MM_CLK_DISP_AXI>,
> +						  <&clk 
IMX8MM_CLK_DISP_APB>;
> +				assigned-clock-parents = <&clk 
IMX8MM_VIDEO_PLL1_OUT>,
> +							 <&clk 
IMX8MM_SYS_PLL2_1000M>,
> +							 <&clk 
IMX8MM_SYS_PLL1_800M>;
> +				assigned-clock-rates = <594000000>, 
<500000000>, <200000000>;
> +				interrupts = <GIC_SPI 5 
IRQ_TYPE_LEVEL_HIGH>;
> +				power-domains = <&disp_blk_ctrl 
IMX8MM_DISPBLK_PD_LCDIF>;
> +				status = "disabled";
> +
> +				port {
> +					lcdif_to_dsim: endpoint {
> +						remote-endpoint = 
<&dsim_from_lcdif>;
> +					};
> +				};
> +			};
> +
> +			mipi_dsi: dsi at 32e10000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8mm-mipi-dsim";
> +				reg = <0x32e10000 0x400>;
> +				clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> +					 <&clk 
IMX8MM_CLK_DSI_PHY_REF>;
> +				clock-names = "bus_clk", "sclk_mipi";
> +				assigned-clocks = <&clk 
IMX8MM_CLK_DSI_CORE>,
> +						  <&clk 
IMX8MM_CLK_DSI_PHY_REF>;
> +				assigned-clock-parents = <&clk 
IMX8MM_SYS_PLL1_266M>,
> +							 <&clk 
IMX8MM_CLK_24M>;
> +				assigned-clock-rates = <266000000>, 
<24000000>;
> +				samsung,pll-clock-frequency = 
<24000000>;

What about samsung,burst-clock-frequency and samsung,esc-clock-frequency? Is 
there is sane default? Do they need to be provided in the board file?

Best regards,
Alexander

> +				interrupts = <GIC_SPI 18 
IRQ_TYPE_LEVEL_HIGH>;
> +				power-domains = <&disp_blk_ctrl 
IMX8MM_DISPBLK_PD_MIPI_DSI>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port at 0 {
> +						reg = <0>;
> +
> +						dsim_from_lcdif: 
endpoint {
> +							remote-
endpoint = <&lcdif_to_dsim>;
> +						};
> +					};
> +				};
> +			};
> +
>  			csi: csi at 32e20000 {
>  				compatible = "fsl,imx8mm-csi", 
"fsl,imx7-csi";
>  				reg = <0x32e20000 0x1000>;


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