[PATCH net-next v2 3/3] net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J784S4 CPSW9G

[Siddharth Vadapalli]

On 03/04/23 16:40, Russell King (Oracle) wrote:
> On Mon, Apr 03, 2023 at 04:31:06PM +0530, Siddharth Vadapalli wrote:
>> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the
>> extra_modes member of the J784S4 SoC data.
>>
>> Additionally, convert the IF statement in am65_cpsw_nuss_mac_config() to
>> SWITCH statement to scale for new modes. Configure MAC control register
>> for supporting USXGMII mode and add MAC_5000FD in the "mac_capabilities"
>> member of struct "phylink_config".
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli at ti.com>
>> ---
>>  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 18 +++++++++++++++---
>>  1 file changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> index 6c118a9abb2f..f4d4f987563c 100644
>> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
>> @@ -1507,10 +1507,20 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>>  	u32 mac_control = 0;
>>  
>>  	if (common->pdata.extra_modes & BIT(state->interface)) {
>> -		if (state->interface == PHY_INTERFACE_MODE_SGMII) {
>> +		switch (state->interface) {
>> +		case PHY_INTERFACE_MODE_SGMII:
>>  			mac_control |= CPSW_SL_CTL_EXT_EN;
>>  			writel(ADVERTISE_SGMII,
>>  			       port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
>> +			break;
>> +
>> +		case PHY_INTERFACE_MODE_USXGMII:
>> +			mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN;
> 
> Following on to my comments on patch 1, with the addition of these
> control bits, you now will want am65_cpsw_nuss_mac_link_down() to
> avoid clearing these bits as well.

Yes, I will ensure this in the v3 series.

Regards,
Siddharth.