[PATCH 1/2] arm64: dts: tqma8mpql: add PCIe support

[Shawn Guo]

On Tue, Oct 18, 2022 at 10:53:29AM +0200, Alexander Stein wrote:
> Add PCIe support on TQMa8MPxL module on MBa8MPxL mainboard.
> 
> Signed-off-by: Alexander Stein <alexander.stein at ew.tq-group.com>
> ---
> This is based on next-20221018 where imp8mp PCIe support has been
> merged.
> 
>  .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts   | 42 ++++++++++++++++++-
>  1 file changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
> index 7bf6f81e87b4..7a32379cd006 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
> @@ -8,6 +8,7 @@
>  
>  #include <dt-bindings/leds/common.h>
>  #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
>  #include <dt-bindings/pwm/pwm.h>
>  #include "imx8mp-tqma8mpql.dtsi"
>  
> @@ -48,6 +49,12 @@ backlight_lvds: backlight {
>  		status = "disabled";
>  	};
>  
> +	clk_xtal25: clk-xtal25 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;
> +	};
> +
>  	gpio-keys {
>  		compatible = "gpio-keys";
>  		pinctrl-names = "default";
> @@ -340,9 +347,16 @@ &gpio4 {
>  			  "", "", "", "",
>  			  "", "", "", "",
>  			  "", "", "DP_IRQ", "DSI_EN",
> -			  "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
> +			  "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",
>  			  "", "", "", "FAN_PWR",
>  			  "RTC_EVENT#", "CODEC_RST#", "", "";
> +
> +	pcie_refclkreq-hog {

Hyphen is more recommended than underscore for node name.

> +		gpio-hog;
> +		gpios = <22 0>;
> +		output-high;
> +		line-name = "PCIE_REFCLK_OE#";
> +	};
>  };
>  
>  &gpio5 {
> @@ -377,6 +391,13 @@ at24c02_54: eeprom at 54 {
>  		pagesize = <16>;
>  		vcc-supply = <&reg_vcc_3v3>;
>  	};
> +
> +	pcieclk: clk at 6a {

Should be clock-controller at 6a?

Shawn

> +		compatible = "renesas,9fgv0241";
> +		reg = <0x6a>;
> +		clocks = <&clk_xtal25>;
> +		#clock-cells = <1>;
> +	};
>  };
>  
>  &i2c4 {
> @@ -407,6 +428,25 @@ &pcf85063 {
>  	interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
>  };
>  
> +&pcie_phy {
> +	fsl,clkreq-unsupported;
> +	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> +	clocks = <&pcieclk 0>;
> +	clock-names = "ref";
> +	status = "okay";
> +};
> +
> +&pcie {
> +	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +		 <&clk IMX8MP_CLK_HSIO_AXI>,
> +		 <&clk IMX8MP_CLK_PCIE_ROOT>;
> +	clock-names = "pcie", "pcie_bus", "pcie_aux";
> +	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> +	assigned-clock-rates = <10000000>;
> +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> +	status = "okay";
> +};
> +
>  &pwm2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pwm2>;
> -- 
> 2.25.1
>