[PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events

[Shang XiaoJing]

Add some core events of hip08 to the corresponding core-imp-def.json.

Signed-off-by: Shang XiaoJing <shangxiaojing at huawei.com>
Acked-by: James Clark <james.clark at arm.com>
---
 .../arm64/hisilicon/hip08/core-imp-def.json   | 132 ++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
index a4a6408639b4..f9a90d6a958d 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -53,6 +53,36 @@
     {
         "ArchStdEvent": "L2D_CACHE_INVAL"
     },
+    {
+        "PublicDescription": "Number of predictable branches predicted by static predictor",
+        "EventCode": "0x1001",
+        "EventName": "IF_BP_PRED_BR_SP",
+        "BriefDescription": "Static predictor predict count"
+    },
+    {
+        "PublicDescription": "Number of mispredicted procedure returns",
+        "EventCode": "0x100d",
+        "EventName": "IF_BP_MISP_BR_RET",
+        "BriefDescription": "Mispredicted procedures"
+    },
+    {
+        "PublicDescription": "Number of mispredicted indirect branches",
+        "EventCode": "0x1010",
+        "EventName": "IF_BP_MISP_BR_IND",
+        "BriefDescription": "Mispredicted indirect branches"
+    },
+    {
+        "PublicDescription": "Number of mispredicted BLR branches",
+        "EventCode": "0x1013",
+        "EventName": "IF_BP_MISP_BR_BLR",
+        "BriefDescription": "Mispredicted BLR branches"
+    },
+    {
+        "PublicDescription": "Number of mispredicted BL branches",
+        "EventCode": "0x1016",
+        "EventName": "IF_BP_MISP_BR_BL",
+        "BriefDescription": "Mispredicted BL branches"
+    },
     {
         "PublicDescription": "Level 1 instruction cache prefetch access count",
         "EventCode": "0x102e",
@@ -77,12 +107,90 @@
         "EventName": "IF_IS_STALL",
         "BriefDescription": "Instruction fetch stall cycles"
     },
+    {
+        "PublicDescription": "Number of times ROB is full",
+        "EventCode": "0x2004",
+        "EventName": "ROB_STALL",
+        "BriefDescription": "ROB stall"
+    },
+    {
+        "PublicDescription": "Number of times PC buffer is full",
+        "EventCode": "0x2005",
+        "EventName": "PCBUF_STALL",
+        "BriefDescription": "PC buffer stall"
+    },
+    {
+        "PublicDescription": "No INT ptag allocated from free list",
+        "EventCode": "0x2006",
+        "EventName": "INT_PTAG_STALL",
+        "BriefDescription": "INT ptag stall"
+    },
+    {
+        "PublicDescription": "No CC ptag allocated from free list",
+        "EventCode": "0x2007",
+        "EventName": "CC_PTAG_STALL",
+        "BriefDescription": "CC ptag stall"
+    },
+    {
+        "PublicDescription": "No VFP ptag allocated from free list",
+        "EventCode": "0x2008",
+        "EventName": "VFP_PTAG_STALL",
+        "BriefDescription": "VFP ptag stall"
+    },
+    {
+        "PublicDescription": "Issue queue of ALU is full",
+        "EventCode": "0x200b",
+        "EventName": "ALU_ISQ_STALL",
+        "BriefDescription": "ALU issue queue stall"
+    },
+    {
+        "PublicDescription": "Issue queue of LSU is full",
+        "EventCode": "0x200c",
+        "EventName": "LSU_ISQ_STALL",
+        "BriefDescription": "LSU issueQ stall"
+    },
+    {
+        "PublicDescription": "Issue queue of FSU is full",
+        "EventCode": "0x200d",
+        "EventName": "FSU_ISQ_STALL",
+        "BriefDescription": "FSU issueQ stall"
+    },
+    {
+        "PublicDescription": "Sync buffer is full",
+        "EventCode": "0x2010",
+        "EventName": "SYNC_STALL",
+        "BriefDescription": "Sync buffer stall"
+    },
+    {
+        "PublicDescription": "LSU nuke flush caused by incorrect data from speculative execution",
+        "EventCode": "0x2012",
+        "EventName": "NUKE_FLUSH",
+        "BriefDescription": "LSU nuke flush"
+    },
+    {
+        "PublicDescription": "OoO ROB flush",
+        "EventCode": "0x2013",
+        "EventName": "OOO_FLUSH",
+        "BriefDescription": "OoO ROB flush"
+    },
     {
         "PublicDescription": "Instructions can receive, but not send",
         "EventCode": "0x2014",
         "EventName": "FETCH_BUBBLE",
         "BriefDescription": "Instructions can receive, but not send"
     },
+    {
+        "PublicDescription": "Cycles of Fetch bubble >= 4",
+        "EventCode": "0x201d",
+        "EventName": "FETCH_BUBBLE_EXCEEDMIW",
+        "BriefDescription": "Cycles of Fetch bubble >= 4"
+    },
+    {
+        "PublicDescription": "SaveOp queue is full",
+        "EventCode": "0x201e",
+        "EventName": "SAVEOP_QUEUE_STALL",
+        "BriefDescription": "SaveOp queue stall"
+    },
     {
         "PublicDescription": "Prefetch request from LSU",
         "EventCode": "0x6013",
@@ -95,18 +203,42 @@
         "EventName": "HIT_ON_PRF",
         "BriefDescription": "Hit on prefetched data"
     },
+    {
+        "PublicDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept",
+        "EventCode": "0x7000",
+        "EventName": "RESOURCE_BOUND",
+        "BriefDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept"
+    },
     {
         "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
         "EventCode": "0x7001",
         "EventName": "EXE_STALL_CYCLE",
         "BriefDescription": "Cycles of that the number of issue ups are less than 4"
     },
+    {
+        "PublicDescription": "No any micro operation is issued & no memstall & executing DIV operation",
+        "EventCode": "0x7002",
+        "EventName": "EXE_STALL_DIV",
+        "BriefDescription": "No any micro operation is issued & no memstall & executing DIV operation"
+    },
+    {
+        "PublicDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation",
+        "EventCode": "0x7003",
+        "EventName": "FSU_STALL",
+        "BriefDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation"
+    },
     {
         "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
         "EventCode": "0x7004",
         "EventName": "MEM_STALL_ANYLOAD",
         "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
     },
+    {
+        "PublicDescription": "No any micro operation is issued and meanwhile any store operation is not resolved",
+        "EventCode": "0x7005",
+        "EventName": "MEM_STALL_ANYSTORE",
+        "BriefDescription": "No any micro operation is issued and meanwhile any store operation is not resolved"
+    },
     {
         "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
         "EventCode": "0x7006",
-- 
2.17.1