Need guidance regarding emulation of GICR_PENDBASER and GICR_PROPBASER registers on Aarch32

[Andre Przywara]

On Tue, 18 Oct 2022 11:38:00 +0100
Ayan Kumar Halder <ayankuma at amd.com> wrote:

Hi Ayan,

> Greetings. I am trying to port Xen on Cortex-R52.

Oh dear, my condolences.

> I am trying to understand whether GICR_PENDBASER and GICR_PROPBASER 
> exist on Aarch32 platform.

Those are GIC MMIO registers, so they exist regardless of which instruction
set the CPU is using. There is really nothing architecture wise that would
restrict access.

> Looking at the definition of the registers in "Arm IHI ID020922", (from 
> my understanding) it seems the registers can be accessed in 64bit mode only.

Not really, the GIC spec says that those registers are 64-bit registers.
What that means is explained in section "12.1.3 GIC memory-mapped
register access", of particular interest is the paragraph starting with:
"In addition, in system where one or more PE supports AArch32: ...."

> Please confirm if my understanding is correct or not.
> 
> This seems unlike GICR_TYPER which might be accessed as two 32 bit 
> registers. The reason being the upper 32bits represent affinity and the 
> lower 32 bits represent everything else.

There is really not much difference access-wise between TYPER and BASER.
You can always access them as two words, and this is the recommended way
to do so on AArch32, or actually in both ISAs. Check out Jean-Philippe's
comment here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/include/asm/arch_gicv3.h#n135

In particular the BASE registers don't require atomic accesses, since they
only become effective later on, as it's not allowed to write to them when
LPIs are enabled. So there is no problem in updating the upper and lower
half in separate steps.

> If GICR_PENDBASER and GICR_PROPBASER are accessible in 64 bit mode only, 
> then we Xen can't emulate them on Aarch32 as ISS is invalid (for ldrd, 
> strd instructions).

If the guest is accessing them using ldrd/strd (which is architecturally
valid, but not easily virtualisable), then you cannot do anything about
it, and would need to change the guest to not do so. See above what Linux
does: always access them in two chunks, so it works everywhere.

Cheers,
Andre

> However, looking at the following commit in kernel, I am a bit confused.
> 
> commit 0aa1de57319c4e023187aca0d59dd593a96459a8
> Author: Andre Przywara <andre.przywara at arm.com>
> Date:   Fri Jul 15 12:43:29 2016 +0100
> 
>      KVM: arm64: vgic: Handle ITS related GICv3 redistributor registers
> 
>      In the GICv3 redistributor there are the PENDBASER and PROPBASER
>      registers which we did not emulate so far, as they only make sense
>      when having an ITS. In preparation for that emulate those MMIO
>      accesses by storing the 64-bit data written into it into a variable
>      which we later read in the ITS emulation.
>      We also sanitise the registers, making sure RES0 regions are respected
>      and checking for valid memory attributes.
> 
> <<<<< code >>>
> REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
> -               vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
> +               vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
>                  VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>          REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
> -               vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
> +               vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
>                  VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
> <<<< code >>>>
> 
> The register regions are defined in arch/arm64/kvm/vgic/vgic-mmio-v3.c 
> and the registers seem accessible in both 64 bit and 32 bit modes.
> Please let me know if GICR_PENDBASER and GICR_PROPBASER are accessible 
> in 32 bit mode.
> 
> Kind regards,
> Ayan