[PATCH] arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock

[Wolfram Sang]

On Fri, Oct 07, 2022 at 05:20:03PM +0200, Geert Uytterhoeven wrote:
> As serial communication requires a clock signal, the High Speed Serial
> Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
> 
> Hence change the clock input for the HSCIF0 Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54.
> 
> Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas at sang-engineering.com>

Do we need to wait for the clarification about the docs mentioned in
another thread?

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