[PATCH 1/2] PCI: armada8k: Add AC5 SoC support

[Bjorn Helgaas]

On Thu, Oct 06, 2022 at 02:11:09PM +0300, Vadym Kochan wrote:
> From: raza <raza at marvell.com>
> 
> pcie-armada8k driver is utilized to serve also AC5.
> Driver assumes interrupt mask registers are located in the same address in
> both CPUs.
> This assumption is incorrect - fix it for AC5.

Rewrap into one paragraph or add blank lines between paragraphs.

> Co-developed-by: Yuval Shaia <yshaia at marvell.com>
> Signed-off-by: Yuval Shaia <yshaia at marvell.com>
> Signed-off-by: raza <raza at marvell.com>

Real name for "raza"?  See this:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v5.18#n407

> +		/* Set the PCIe master AxCache attributes */
> +		dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
> +		dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);

Rewrap to fit in 80 columns like the rest of the file.

> +static u32 ac5_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> +			     u32 reg, size_t size)
> +{
> +	u32 val;
> +
> +	/* Handle AC5 ATU access */
> +	if ((reg & ~0xfffff) == 0x300000) {
> +		reg &= 0xfffff;
> +		reg = 0xc000 | (0x200 * (reg >> 9)) | (reg & 0xff);
> +	} else if ((reg & 0xfffff000) == PCIE_VENDOR_REGS_OFFSET)
> +		reg += 0x8000; /* PCIE_VENDOR_REGS_OFFSET in ac5 is 0x10000 */

There are lots of magic numbers here; looks like there should be some
#defines or something.

Bjorn