[PATCH v2] kernel: arm64: add Spectre-V2 mitigation cb for NV CPUs

[Rich Wiley]

NVIDIA cores can flush indirect branch predictors with a sysreg write
that can be done from the kernel without the need for a FW call.

Given that NVIDIA cores are not susceptible to CVE-2022-23960 and FW
mitigation is not required for CVE-2017-5715, ATF can report via
SMCCC_ARCH_WORKAROUND_3 that FW mitigation is not required for either.

Fixes: commit ba2689234be9 ("arm64: entry: Add vectors that have the bhb
mitigation sequences")


Signed-off-by: Rich Wiley <rwiley at nvidia.com>
---
 arch/arm64/kernel/proton-pack.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
index 40be3a7c2c53..0de77b0ff8d4 100644
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@ -258,14 +258,26 @@ static noinstr void qcom_link_stack_sanitisation(void)
 		     : "=&r" (tmp));
 }
 
+/* Called during entry so must be noinstr */
+static noinstr void nvidia_indirect_branch_pred_flush(void)
+{
+	asm volatile("msr s3_0_c15_c0_6, %0" :: "r" (0x1UL));
+	isb();
+}
+
 static bp_hardening_cb_t spectre_v2_get_sw_mitigation_cb(void)
 {
 	u32 midr = read_cpuid_id();
-	if (((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR) &&
-	    ((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR_V1))
-		return NULL;
+	if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
+	    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
+		return qcom_link_stack_sanitisation;
+
+	if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_NVIDIA_DENVER) ||
+	    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_NVIDIA_CARMEL))
+		return nvidia_indirect_branch_pred_flush;
+
+	return NULL;
 
-	return qcom_link_stack_sanitisation;
 }
 
 static enum mitigation_state spectre_v2_enable_fw_mitigation(void)
-- 
2.17.1