[PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema

[Krzysztof Kozlowski]

On 03/10/2022 15:24, Rob Herring wrote:
> On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote:
>> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
>> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
>> are individual IRQs for each ECC and DFI events. The dedicated scrubber
>> clock source is absent since it's fully synchronous to the core clock.
>> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
>> registers space.
>>
>> Signed-off-by: Serge Semin <Sergey.Semin at baikalelectronics.ru>
>> Reviewed-by: Rob Herring <robh at kernel.org>
>>
>> ---
>>
>> Changelog v2:
>> - Keep the alphabetically ordered compatible strings list. (@Krzysztof)
>> - Fix grammar nitpicks in the patch log. (@Krzysztof)
>> - Drop the PHY CSR region. (@Rob)
>> - Move the device bindings to the separate DT-schema.
>> ---
>>  .../memory-controllers/baikal,bt1-ddrc.yaml   | 91 +++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml
>>
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml

This is result of patch #1 failing to apply:

https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/

The bindings look ok, but anyway it is a merge window now.


Best regards,
Krzysztof