[PATCH v2] arm64: mm: Align PGDs to at least 64 bytes

[Marc Zyngier]

On Tue, 29 Nov 2022 14:30:12 +0000,
Ard Biesheuvel <ardb at kernel.org> wrote:
> 
> My copy of the ARM ARM (DDI 0487I.a) no longer describes the 64 byte
> minimum alignment of root page tables as being conditional on whether
> 52-bit physical addressing is supported and enabled, even though I seem
> to remember that this was the case formerly (and our code suggests the
> same).
> 
> Section D17.2.144 "TTBR0_EL1, Translation Table Base Register 0 (EL1)"
> contains the following wording:
> 
>   ----Note----
>   A translation table is required to be aligned to the size of the
>   table. If a table contains fewer than eight entries, it must be
>   aligned on a 64 byte address boundary
> 
> So align pgd_t[] allocations to 64 bytes. Note that this change only
> affects 16k/4 levels configurations, which are unlikely to be in wide
> use.
> 
> Signed-off-by: Ard Biesheuvel <ardb at kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>

After the VTTBR discussion, and to be extra sure of this, I reached
out to ARM and asked for clarification.

As it turns out, the omission of the "> 48 bits" restriction is an
unfortunate specification bug, and the old behaviour still applies
(Rule KBLCR is also wrong).

Can't wait for the next revision! ;-)

	M.

-- 
Without deviation from the norm, progress is not possible.