[PATCH] arm64: mm: Align PGDs to at least 64 bytes

[Ard Biesheuvel]

On Mon, 28 Nov 2022 at 18:50, Catalin Marinas <catalin.marinas at arm.com> wrote:
>
> On Tue, Nov 22, 2022 at 05:56:18PM +0100, Ard Biesheuvel wrote:
> > My copy of the ARM ARM (DDI 0487G.a) no longer describes the 64 byte
>
> G.a is nearly two years old. You may want to upgrade to H.a ;).
>
> > minimum alignment of root page tables as being conditional on whether
> > 52-bit physical addressing is supported and enabled, even though I seem
> > to remember that this was the case formerly (and our code suggests the
> > same).
>
> The wording in the ARM ARM implies that it's only needed if we go beyond
> 48 bits for the base address:
>
>   A translation table must be aligned to the size of the table, except
>   that when using a translation table base address larger than 48 bits
>   the minimum alignment of a table containing fewer than eight entries
>   is 64 bytes.
>
> But I'm fine with the patch, always forcing the 64 byte alignment. With
> the 'max_t' instead of 'max' (or whatever solves Anshuman's error):
>
> Acked-by: Catalin Marinas <catalin.marinas at arm.com>

Right, so it appears they backpedaled on that.

The distinction is kind of important depending on whether we want to
fall back to 47 or 48 bits of VA space on on 16k granule configs with
LPA2 running on systems that lack LPA2 support.

If we want to fall back to 48 bits, TTBR1 must be incremented to point
to the entries describing the 48-bit VA space inside a table
dimensioned for 52 bits, and in this case, those entries can simply
not appear on a 64 byte aligned boundary.