[PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP

[Peng Fan]

> Subject: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data
> in OCOTP
> 
> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
> calibration values in OCOTP. Add the OCOTP calibration values phandle so the
> TMU driver can perform this programming.
> 
> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2
> uses 4.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>

Reviewed-by: Peng Fan <peng.fan at nxp.com>

> ---
> Cc: Adam Ford <aford173 at gmail.com>
> Cc: Alice Guo <alice.guo at nxp.com>
> Cc: Amit Kucheria <amitk at kernel.org>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
> Cc: Li Jun <jun.li at nxp.com>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: Markus Niebel <Markus.Niebel at ew.tq-group.com>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
> Cc: Rafael J. Wysocki <rafael at kernel.org>
> Cc: Richard Cochran <richardcochran at gmail.com>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: Zhang Rui <rui.zhang at intel.com>
> Cc: devicetree at vger.kernel.org
> To: linux-pm at vger.kernel.org
> To: linux-arm-kernel at lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
>  3 files changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 513c2de0caa15..0cd7fff47c44d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -496,6 +496,8 @@ tmu: tmu at 30260000 {
>  				compatible = "fsl,imx8mm-tmu";
>  				reg = <0x30260000 0x10000>;
>  				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
> +				nvmem-cells = <&tmu_calib>;
> +				nvmem-cell-names = "calib";
>  				#thermal-sensor-cells = <0>;
>  			};
> 
> @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
>  					reg = <0x10 4>;
>  				};
> 
> +				tmu_calib: calib at 3c { /* 0x4f0 */
> +					reg = <0x3c 4>;
> +				};
> +
>  				fec_mac_address: mac-address at 90 { /*
> 0x640 */
>  					reg = <0x90 6>;
>  				};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 068f599cdf757..5eef9b274edde 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -498,6 +498,8 @@ tmu: tmu at 30260000 {
>  				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-
> tmu";
>  				reg = <0x30260000 0x10000>;
>  				clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
> +				nvmem-cells = <&tmu_calib>;
> +				nvmem-cell-names = "calib";
>  				#thermal-sensor-cells = <0>;
>  			};
> 
> @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
>  					reg = <0x10 4>;
>  				};
> 
> +				tmu_calib: calib at 3c { /* 0x4f0 */
> +					reg = <0x3c 4>;
> +				};
> +
>  				fec_mac_address: mac-address at 90 { /*
> 0x640 */
>  					reg = <0x90 6>;
>  				};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index ddcd5e23ba47d..0173e394ad4d8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -380,6 +380,8 @@ tmu: tmu at 30260000 {
>  				compatible = "fsl,imx8mp-tmu";
>  				reg = <0x30260000 0x10000>;
>  				clocks = <&clk
> IMX8MP_CLK_TSENSOR_ROOT>;
> +				nvmem-cells = <&tmu_calib>;
> +				nvmem-cell-names = "calib";
>  				#thermal-sensor-cells = <1>;
>  			};
> 
> @@ -454,6 +456,10 @@ eth_mac1: mac-address at 90 { /* 0x640 */
>  				eth_mac2: mac-address at 96 { /* 0x658 */
>  					reg = <0x96 6>;
>  				};
> +
> +				tmu_calib: calib at 264 { /* 0xd90-0xdc0 */
> +					reg = <0x264 0x10>;
> +				};
>  			};
> 
>  			anatop: clock-controller at 30360000 {
> --
> 2.35.1