[PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation
Marek Vasut
marex at denx.de
Sat Nov 26 14:47:38 PST 2022
The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.
Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: Adam Ford <aford173 at gmail.com>
Cc: Alice Guo <alice.guo at nxp.com>
Cc: Amit Kucheria <amitk at kernel.org>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
Cc: Li Jun <jun.li at nxp.com>
Cc: Lucas Stach <l.stach at pengutronix.de>
Cc: Markus Niebel <Markus.Niebel at ew.tq-group.com>
Cc: NXP Linux Team <linux-imx at nxp.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
Cc: Rafael J. Wysocki <rafael at kernel.org>
Cc: Richard Cochran <richardcochran at gmail.com>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Shawn Guo <shawnguo at kernel.org>
Cc: Zhang Rui <rui.zhang at intel.com>
Cc: devicetree at vger.kernel.org
To: linux-pm at vger.kernel.org
To: linux-arm-kernel at lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++----
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++---
4 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 423cb36cbcd53..513c2de0caa15 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -563,15 +563,28 @@ ocotp: efuse at 30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id at 4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mm_uid: unique-id at 4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade at 10 {
+ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address at 90 {
+ fec_mac_address: mac-address at 90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 312e3abc35ea8..068f599cdf757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -564,15 +564,28 @@ ocotp: efuse at 30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id at 4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mn_uid: unique-id at 4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade at 10 {
+ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address at 90 {
+ fec_mac_address: mac-address at 90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9459ed21b243..ddcd5e23ba47d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -426,19 +426,32 @@ ocotp: efuse at 30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mp_uid: unique-id at 8 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x8 0x8> describes fuses 0x420 and
+ * 0x430).
+ */
+ imx8mp_uid: unique-id at 8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
- cpu_speed_grade: speed-grade at 10 {
+ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
reg = <0x10 4>;
};
- eth_mac1: mac-address at 90 {
+ eth_mac1: mac-address at 90 { /* 0x640 */
reg = <0x90 6>;
};
- eth_mac2: mac-address at 96 {
+ eth_mac2: mac-address at 96 { /* 0x658 */
reg = <0x96 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2b6d3f4ff5d93..8a2ec90b493d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -593,15 +593,28 @@ ocotp: efuse at 30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mq_uid: soc-uid at 4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mq_uid: soc-uid at 4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade at 10 {
+ cpu_speed_grade: speed-grade at 10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address at 90 {
+ fec_mac_address: mac-address at 90 { /* 0x640 */
reg = <0x90 6>;
};
};
--
2.35.1
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