[RFC PATCH 0/7] arm64: Enable LPA2 support for 16k pages

[Ard Biesheuvel]

Enable support for LPA2 when running with 16k pages. Unlike with 4k
pages, this does not require adding support for 5 level paging, but
beyond that, there is no fundamental difference between LPA2 support on
4k or 16k pages.

There are a few rough edges that make this less straight-forward than it
was to enable LVA on 64k pages: even though also in this case, we can
rely on statically sized root level page tables, we cannot advance the
TTBR1 pointer to the pgdir entry that covers the start of the 48-bit
addressable like we do on LVA, as the resulting address is not 64 byte
aligned, which is a requirement for TTBR registers.

Another slight complication is that the repurposed physical address bits
in the page table descriptors were not RES0 before, and so there is now
a big global switch (called TCR.DS) which controls how all page table
descriptors are interpreted. This requires some extra care in the PTE
conversion helpers, and additional handling in the boot code to ensure
that we set TCR.DS safely if supported (and not overridden)

This series applies onto some of my previous work that is still in
flight, so these patches will not apply in isolation. Complete branch
can be found here:
https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/log/?h=arm64-16k-lpa2

Tested on QEMU with -cpu max and lpa2 both off and on, as well as using
the arm64.nolva override kernel command line parameter. Note that this
requires a QEMU patch that has not been merged yet:
https://lore.kernel.org/qemu-devel/20221116170316.259695-1-ardb@kernel.org/

Cc: Marc Zyngier <maz at kernel.org>
Cc: Will Deacon <will at kernel.org>
Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Kees Cook <keescook at chromium.org>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Mark Brown <broonie at kernel.org>
Cc: Anshuman Khandual <anshuman.khandual at arm.com>
Cc: Richard Henderson <richard.henderson at linaro.org>

Ard Biesheuvel (7):
  arm64: ptdump: Disregard unaddressable VA space
  arm64: mm: Disable all 52-bit virtual addressing support with
    arm64.nolva
  arm64: mm: Wire up TCR.DS bit to PTE shareability fields
  arm64: mm: Support use of 52-bit pgdirs on 48-bit/16k systems
  arm64: mm: Add LPA2 support to phys<->pte conversion routines
  arm64: Enable LPA2 at boot if supported by the system
  arm64: Enable 52-bit virtual addressing for 16k granule configs

 arch/arm64/Kconfig                     |   6 +-
 arch/arm64/include/asm/assembler.h     |  33 ++-----
 arch/arm64/include/asm/cpufeature.h    |   1 +
 arch/arm64/include/asm/mmu.h           |  18 ++++
 arch/arm64/include/asm/pgtable-hwdef.h |  11 ++-
 arch/arm64/include/asm/pgtable-prot.h  |  18 +++-
 arch/arm64/include/asm/pgtable.h       |   5 +-
 arch/arm64/kernel/cpufeature.c         |  27 ++++-
 arch/arm64/kernel/image-vars.h         |   3 +
 arch/arm64/kernel/pi/idreg-override.c  |  26 +++++
 arch/arm64/kernel/pi/map_kernel.c      | 103 +++++++++++++++++++-
 arch/arm64/mm/mmap.c                   |   4 +
 arch/arm64/mm/mmu.c                    |   2 +
 arch/arm64/mm/proc.S                   |  13 +++
 arch/arm64/mm/ptdump.c                 |   4 +-
 15 files changed, 229 insertions(+), 45 deletions(-)

-- 
2.35.1