[External] : [RFC PATCH v2 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2

[Jing Zhang]

在 2022/11/14 下午8:59, John Garry 写道:
> On 14/11/2022 07:41, Jing Zhang wrote:
>> The calculation formula of topdown L1 is from the document:
>> https://urldefense.com/v3/__https://documentation-service.arm.com/static/60250c7395978b529036da86?token=__;!!ACWV5N9M2RV99hQ!Ll-Jgvfs0LitTCU-hC6i6BKBVJfhke-pbQq2VoO-gmuSAcglQ3ZqMVMd2r0An_5a3ZDPYmn8zXuCrpUbehwnLHplVQ$  
> 
> So since this is a from "standard" document, did you consider putting these as an arch std event? I think arch std events would work for metrics, like they do for regular events.
> 

I didn't find out how to put the metric as an arch std event, it would be best if you could provide me with an example in the upstream code,
thank you very much.

>>
>> However, due to the wrong count of stall_slot and stall_slot_frontend
>> in neoverse-n2, the real stall_slot and real stall_slot_frontend need
>> to subtract cpu_cycles, so when calculating the topdownL1 metrics,
>> stall_slot and stall_slot_frontend are corrected.
> 
> Is there a reference to this? It would be indeed useful to pass a link to the n2 doc as these metrics are not part of the arm64 arm. At least I assume that they are not there.
> 

You are right, I need to add a doc link. ARM has released the n2 ERRATA document about the incorrect count of stall_slot and stall_slot_frontend,
and provides a workaround to get the correct value.
Link: https://developer.arm.com/documentation/SDEN1982442/1200/?lang=en

>>
>> Since neoverse-n2 does not yet support topdown L2, metricgroups such
>> as Cache, TLB, Branch, InstructionsMix, and PEutilization will be
>> added to further analysis of performance bottlenecks in the following
>> patches.
>>
> 
> 
> Thanks,
> John
Best Regards,
Jing