[PATCH 3/5] arm64: dts: renesas: r8a779g0: Add CPUIdle support

[Geert Uytterhoeven]

Support CPUIdle for ARM Cortex-A76 on R-Car V4H.

Based on patches in the BSP by Tho Vu and Vincent Bryce.

Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index dc5f27c114a7ad96..21baa4936b4fba3e 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -45,6 +45,7 @@ a76_0: cpu at 0 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_1: cpu at 100 {
@@ -54,6 +55,7 @@ a76_1: cpu at 100 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_2: cpu at 10000 {
@@ -63,6 +65,7 @@ a76_2: cpu at 10000 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_3: cpu at 10100 {
@@ -72,8 +75,22 @@ a76_3: cpu at 10100 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+	       };
+
 		L3_CA76_0: cache-controller-0 {
 			compatible = "cache";
 			power-domains = <&sysc R8A779G0_PD_A2E0D0>;
-- 
2.25.1