[PATCH 07/20] arm64: dts: Update cache properties for freescale

[Chester Lin]

Hi Shawn,

On Fri, Nov 11, 2022 at 10:55:53AM +0800, Shawn Guo wrote:
> On Mon, Oct 31, 2022 at 10:19:51AM +0100, Pierre Gondois wrote:
> > The DeviceTree Specification v0.3 specifies that the cache node
> > 'compatible' and 'cache-level' properties are 'required'. Cf.
> > s3.8 Multi-level and Shared Cache Nodes
> > 
> > The recently added init_of_cache_level() function checks
> > these properties. Add them if missing.
> > 
> > Signed-off-by: Pierre Gondois <pierre.gondois at arm.com>
> 
> Looks good to me.  Should I pick it up on IMX tree, or it needs to go as
> part of the series (via other tree)?
> 
> Shawn
> 

The change for s32g2 looks good to me. I would be grateful if you could pick
this patch to the IMX tree. Thanks!

Reviewed-by: Chester Lin <clin at suse.com>

> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
> >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
> >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi     | 1 +
> >  arch/arm64/boot/dts/freescale/s32g2.dtsi       | 2 ++
> >  arch/arm64/boot/dts/freescale/s32v234.dtsi     | 2 ++
> >  8 files changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 5627dd7734f3..ed0cc1a5d17e 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -46,6 +46,7 @@ cpu1: cpu at 1 {
> >  
> >  		l2: l2-cache {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> > index ca3d5a90d6d4..c8b1202d2584 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> > @@ -83,6 +83,7 @@ cpu3: cpu at 3 {
> >  
> >  		l2: l2-cache {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > index feab604322cf..4590bdc076b7 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > @@ -78,6 +78,7 @@ cpu3: cpu at 3 {
> >  
> >  		l2: l2-cache {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> > index 6f6667b70028..2a7e13b6ef8a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> > @@ -95,18 +95,22 @@ cpu7: cpu at 301 {
> >  
> >  	cluster0_l2: l2-cache0 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster1_l2: l2-cache1 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster2_l2: l2-cache2 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster3_l2: l2-cache3 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	CPU_PW20: cpu-pw20 {
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > index c3dc38188c17..c12c86915ec8 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > @@ -95,18 +95,22 @@ cpu7: cpu at 301 {
> >  
> >  	cluster0_l2: l2-cache0 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster1_l2: l2-cache1 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster2_l2: l2-cache2 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	cluster3_l2: l2-cache3 {
> >  		compatible = "cache";
> > +		cache-level = <2>;
> >  	};
> >  
> >  	CPU_PW20: cpu-pw20 {
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > index 60c1b018bf03..187353458673 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > @@ -50,6 +50,7 @@ A35_1: cpu at 1 {
> >  
> >  		A35_L2: l2-cache0 {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index 824d401e7a2c..d8c82da88ca0 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -52,10 +52,12 @@ cpu3: cpu at 101 {
> >  
> >  		cluster0_l2: l2-cache0 {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  
> >  		cluster1_l2: l2-cache1 {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> > index ba0b5305d481..3e306218d533 100644
> > --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> > @@ -61,10 +61,12 @@ cpu3: cpu at 101 {
> >  
> >  		cluster0_l2_cache: l2-cache0 {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  
> >  		cluster1_l2_cache: l2-cache1 {
> >  			compatible = "cache";
> > +			cache-level = <2>;
> >  		};
> >  	};
> >  
> > -- 
> > 2.25.1
> >