[PATCH 4/4] arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC

[Sriranjani P]

The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in
FSYS0 block and other in PERIC block.

Adds device tree node for Ethernet in PERIC Block and enables the same for
FSD platform.

Cc: Rob Herring <robh+dt at kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
Cc: Richard Cochran <richardcochran at gmail.com>
Cc: devicetree at vger.kernel.org
Signed-off-by: Pankaj Dubey <pankaj.dubey at samsung.com>
Signed-off-by: Jayati Sahu <jayati.sahu at samsung.com>
Signed-off-by: Sriranjani P <sriranjani.p at samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts      |  9 ++++
 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 +++++++++++++++++++++
 arch/arm64/boot/dts/tesla/fsd.dtsi         | 58 ++++++++++++++++++++++
 3 files changed, 123 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 42bf25c680e2..328db875667a 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -39,6 +39,15 @@
 	};
 };
 
+&ethernet_1 {
+	status = "okay";
+
+	fixed-link {
+		speed=<1000>;
+		full-duplex;
+	};
+};
+
 &fin_pll {
 	clock-frequency = <24000000>;
 };
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index 8c7e43085a2b..94ef5392ad9c 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -395,6 +395,62 @@
 		samsung,pin-pud = <FSD_PIN_PULL_UP>;
 		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
+
+	eth1_tx_clk: eth1-tx-clk-pins {
+		samsung,pins = "gpf2-0";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_tx_data: eth1-tx-data-pins {
+		samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_tx_ctrl: eth1-tx-ctrl-pins {
+		samsung,pins = "gpf2-5";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_phy_intr: eth1-phy-intr-pins {
+		samsung,pins = "gpf2-6";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+	};
+
+	eth1_rx_clk: eth1-rx-clk-pins {
+		samsung,pins = "gpf3-0";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_rx_data: eth1-rx-data-pins {
+		samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_rx_ctrl: eth1-rx-ctrl-pins {
+		samsung,pins = "gpf3-5";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+	};
+
+	eth1_mdio: eth1-mdio-pins {
+		samsung,pins = "gpf3-6", "gpf3-7";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+	};
 };
 
 &pinctrl_pmu {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 2495928b71dc..e63c1f8fa6ca 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -33,6 +33,7 @@
 		spi1 = &spi_1;
 		spi2 = &spi_2;
 		eth0 = &ethernet_0;
+		eth1 = &ethernet_1;
 	};
 
 	cpus {
@@ -898,6 +899,63 @@
 			status = "disabled";
 			phy-mode = "rgmii";
 		};
+
+		ethernet_1: ethernet at 14300000 {
+			compatible = "tesla,dwc-qos-ethernet-4.21";
+			reg = <0x0 0x14300000 0x0 0x10000>;
+			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =
+				/* ptp ref clock */
+				<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
+				/* aclk clocks */
+				<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
+				/* hclk clocks */
+				<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
+				/* rgmii clocks */
+				<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
+				/* rxi clocks */
+				<&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
+				/* eqos d-bus clocks */
+				<&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
+				/* eqos p-bus clocks */
+				<&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
+				/* eqos peric clock mux */
+				<&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
+				/* eqos peric phy rxclock */
+				<&clock_peric PERIC_EQOS_PHYRXCLK>,
+				/* internal peric rgmii clk */
+				<&clock_peric PERIC_DOUT_RGMII_CLK>;
+			clock-names =
+				/* ptp ref clocks */
+				"ptp_ref",
+				/* aclk clocks */
+				"master_bus",
+				/* hclk clocks */
+				"slave_bus",
+				/* rgmii clk */
+				"tx",
+				/* rxi clocks */
+				"rx",
+				/* eqos dbus clocks */
+				"master2_bus",
+				/* eqos pbus clocks */
+				"slave2_bus",
+				/* rgmii clock mux */
+				"eqos_rxclk_mux",
+				/* rgmii phy rx clock */
+				"eqos_phyrxclk",
+				/* internal peric rgmii clk */
+				"dout_peric_rgmii_clk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
+				<&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
+				<&eth1_rx_ctrl>, <&eth1_mdio>;
+			local-mac-address = [45 54 48 31 4d 43];
+			rx-clock-skew = <&sysreg_peric 0x10 0x0>;
+			iommus = <&smmu_peric 0x0 0x1>;
+			status = "disabled";
+			phy-mode = "rgmii";
+		};
 	};
 };
 
-- 
2.17.1