[PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
Alexander Stein
alexander.stein at ew.tq-group.com
Thu Nov 3 00:58:01 PDT 2022
Am Mittwoch, 2. November 2022, 22:22:46 CET schrieb Marek Vasut:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: Fabio Estevam <festevam at denx.de>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Richard Zhu <hongxing.zhu at nxp.com>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: NXP Linux Team <linux-imx at nxp.com>
> To: linux-arm-kernel at lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi | 1 -
> arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 6 +++---
> arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> 15 files changed, 28 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index
> 03266bd90a06b..f3cb7e27799e7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> @@ -241,9 +241,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk_gated>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index
> cd08430126887..a99cdb9630ef8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> @@ -905,9 +905,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcieclk 0>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index
> 7d6317d95b131..7d004ffe7d4a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -358,9 +358,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi index
> 44e87b1568e79..1bbf1c1521415 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> @@ -212,7 +212,6 @@ &pcie0 {
> reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
> clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
> <&clk IMX8MM_CLK_PCIE1_AUX>;
> - clock-names = "pcie", "pcie_bus", "pcie_aux";
> fsl,max-link-speed = <1>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk
> IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index
> 4a3df2b77b0be..4344d7b521911 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> @@ -175,9 +175,9 @@ &pcie0 {
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
> <&clk IMX8MM_SYS_PLL2_250M>;
> assigned-clock-rates = <10000000>, <250000000>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&clk IMX8MM_CLK_PCIE1_PHY>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> + <&clk IMX8MM_CLK_PCIE1_PHY>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie>;
> reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index
> 7e0aeb2db3054..65b99e201d8f7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> @@ -65,9 +65,8 @@ &pcie_phy {
>
> &pcie0 {
> reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index
> c557dbf4dcd60..0ce60ad9c7d50 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> @@ -120,9 +120,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index
> 41d0de6a7027b..570992a52b759 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> @@ -142,9 +142,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index
> 244ef8d6cc688..47ba0be554fa2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> @@ -162,9 +162,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index
> 750a1f07ecb7a..2bd117cefef84 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -702,9 +702,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index
> 421fd0004eafc..3e203ace11da2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> @@ -622,9 +622,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index
> 8ce562246a08e..e7c79a82ab33d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> @@ -557,9 +557,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index
> eceed9816f5dc..2c44ceefa6ae7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> @@ -618,9 +618,8 @@ &pcie0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&pcie0_refclk>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>,
> assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> <&clk IMX8MM_CLK_PCIE1_CTRL>;
> assigned-clock-rates = <10000000>, <250000000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index
> 0d454e0e2f7c8..ac7af722f240d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -654,9 +654,8 @@ &pcie0 {
> <&clk IMX8MM_SYS_PLL2_250M>;
> assigned-clock-rates = <10000000>, <250000000>;
> clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> - <&clk IMX8MM_CLK_PCIE1_AUX>,
> - <&clk IMX8MM_CLK_PCIE1_PHY>;
> - clock-names = "pcie", "pcie_aux", "pcie_bus";
> + <&clk IMX8MM_CLK_PCIE1_PHY>,
> + <&clk IMX8MM_CLK_PCIE1_AUX>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pcie0>;
> /* PCIE_1_RESET# (SODIMM 244) */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index
> ac51ee6c28fe1..c11fcfc8e58dc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1283,6 +1283,7 @@ pcie0: pcie at 33800000 {
> <0 0 0 4 &gic GIC_SPI 122
IRQ_TYPE_LEVEL_HIGH>;
> fsl,max-link-speed = <2>;
> linux,pci-domain = <0>;
> + clock-names = "pcie", "pcie_bus", "pcie_aux";
> power-domains = <&pgc_pcie>;
> resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
> <&src
IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
For imx8mm.dtsi and imx8mm-tqma8mqml-mba8mx.dts:
Reviewed-by: Alexander Stein <alexander.stein at ew.tq-group.com>
Thanks
Alexander
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