[PATCH 3/4] arm64: dts: exynosautov9: add secondary ufs devices
Chanho Park
chanho61.park at samsung.com
Tue May 31 05:19:12 PDT 2022
Add ufs_1_phy and ufs_1 for secondary ufs hci controller and phy
device.
Signed-off-by: Chanho Park <chanho61.park at samsung.com>
---
arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 3e23db8f09d9..c146271af477 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -380,6 +380,17 @@ ufs_0_phy: ufs0-phy at 17e04000 {
status = "disabled";
};
+ ufs_1_phy: ufs0-phy at 17f04000 {
+ compatible = "samsung,exynosautov9-ufs-phy";
+ reg = <0x17f04000 0xc00>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
+ #phy-cells = <0>;
+ clocks = <&xtcxo>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
ufs_0: ufs0 at 17e00000 {
compatible ="samsung,exynosautov9-ufs";
@@ -400,6 +411,27 @@ ufs_0: ufs0 at 17e00000 {
samsung,sysreg = <&syscon_fsys2 0x710>;
status = "disabled";
};
+
+ ufs_1: ufs0 at 17f00000 {
+ compatible ="samsung,exynosautov9-ufs";
+
+ reg = <0x17f00000 0x100>, /* 0: HCI standard */
+ <0x17f01100 0x410>, /* 1: Vendor-specific */
+ <0x17f80000 0x8000>, /* 2: UNIPRO */
+ <0x17de0000 0x2200>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
+ <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
+ phys = <&ufs_1_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&syscon_fsys2 0x714>;
+ status = "disabled";
+ };
};
};
--
2.36.1
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