[PATCH RFC] arm64/sysregs: Align field names in ID_AA64DFR0_EL1 with architecture

[Catalin Marinas]

On Wed, May 25, 2022 at 09:46:13AM +0100, Mark Rutland wrote:
> On Wed, May 18, 2022 at 03:57:50PM +0100, Mark Brown wrote:
> > The naming scheme the architecture uses for the fields in ID_AA64DFR0_EL1
> > does not align well with kernel conventions, using as it does a lot of
> > MixedCase in various arrangements. In preparation for automatically
> > generating the defines for this register rename the defines used to match
> > what is in the architecture.
> > 
> > Signed-off-by: Mark Brown <broonie at kernel.org>
> > ---
> > 
> > I am not entirely convinced if the best approach here is to deviate from
> > the kernel naming convention as this does or to follow the architecture
> > as we've decided in other cases, I don't really mind but would like some
> > feedback before going ahead and sorting out the remaining issues with
> > this register.
> 
> It's unfortunate the architecture itself doesn't follow a consistent pattern.
> :/
> 
> I don't personally have strong feelings here. I'm happy with either:
> 
> (a) Matching the case to the architectural names, even if that means some
>     fields are MixedCase, as with this patch
> 
> (b) Always using ALLCAPS for ID reg field definitions.
> 
> Catalin/Marc/Will, any preference?

I don't have a preference either. We have some limited mixed case places
but mostly with a single 'n'. As we go for the automatic generation of
these macros, it makes some sense to keep them aligned with the
architecture. My only worry with (a) is the diffstat and potential
conflicts.

-- 
Catalin