[PATCH] spi: atmel-quadspi: Add support for sama7g5 QSPI

[Claudiu.Beznea at microchip.com]

Hi, Tudor,

On 14.12.2021 15:34, Tudor Ambarus wrote:
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> 
> The sama7g5 QSPI controller uses dedicated clocks for the
> QSPI Controller Interface and the QSPI Controller Core, and
> requires synchronization before accessing registers or bit
> fields.
> 
> QSPI_SR.SYNCBSY must be zero before accessing any of the bits:
> QSPI_CR.QSPIEN, QSPI_CR.QSPIDIS, QSPI_CR.SRFRSH, QSPI_CR.SWRST,
> QSPI_CR.UPDCFG, QSPI_CR.STTFR, QSPI_CR.RTOUT, QSPI_CR.LASTXFER.
> 
> Also, the QSPI controller core configuration can be updated by
> writing the QSPI_CR.UPDCFG bit to ‘1’. This is needed by the
> following registers: QSPI_MR, QSPI_SCR, QSPI_IAR, QSPI_WICR,
> QSPI_IFR, QSPI_RICR, QSPI_SMR, QSPI_SKR,QSPI_REFRESH, QSPI_WRACNT
> QSPI_PCALCFG.
> 
> The Octal SPI supports frequencies up to 200 MHZ DDR. The need
> for output impedance calibration arises. To avoid the degradation
> of the signal quality, a PAD calibration cell is used to adjust
> the output impedance to the driven I/Os.
> 
> The transmission flow requires different sequences for setting
> the configuration and for the actual transfer, than what is in
> the sama5d2 and sam9x60 versions of the IP. Different interrupts
> are handled. aq->ops->set_cfg() and aq->ops->transfer() are
> introduced to help differentiating the flows.
> 
> Tested single and octal SPI mode with mx66lm1g45g.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus at microchip.com>
> ---
>  drivers/spi/atmel-quadspi.c | 921 ++++++++++++++++++++++++++++++++++--
>  1 file changed, 869 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index 92d9610df1fd..8980a729dd53 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -11,11 +11,15 @@
>   * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
>   */

[ cut ]

> +}
> +
>  static int atmel_qspi_remove(struct platform_device *pdev)
>  {
>         struct spi_controller *ctrl = platform_get_drvdata(pdev);
>         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
> 
>         spi_unregister_controller(ctrl);
> +
> +       if (aq->caps->has_gclk)
> +               return atmel_qspi_sama7g5_suspend(aq);
> +
> +       if (aq->caps->has_dma)
> +               atmel_qspi_dma_release(aq);
> +

The order here should be reversed. Otherwise DMA channel will not be
released in case aq->caps->has_gclk is true.

Thank you,
Claudiu Beznea