[PATCH] ARM: mm: Kconfig: Fix indentation

[Juerg Haefliger]

The convention for indentation seems to be a single tab. Help text is
further indented by an additional two whitespaces. Fix the lines that
violate these rules.

Signed-off-by: Juerg Haefliger <juergh at canonical.com>
---
 arch/arm/mm/Kconfig | 48 ++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d30ee26ccc87..950f67220caf 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -123,13 +123,13 @@ config CPU_ARM925T
 	select CPU_PABRT_LEGACY
 	select CPU_THUMB_CAPABLE
 	select CPU_TLB_V4WBI if MMU
- 	help
- 	  The ARM925T is a mix between the ARM920T and ARM926T, but with
+	help
+	  The ARM925T is a mix between the ARM920T and ARM926T, but with
 	  different instruction and data caches. It is used in TI's OMAP
- 	  device family.
+	  device family.
 
- 	  Say Y if you want support for the ARM925T processor.
- 	  Otherwise, say N.
+	  Say Y if you want support for the ARM925T processor.
+	  Otherwise, say N.
 
 # ARM926T
 config CPU_ARM926T
@@ -838,19 +838,19 @@ config HARDEN_BRANCH_PREDICTOR
 	depends on CPU_SPECTRE
 	default y
 	help
-	   Speculation attacks against some high-performance processors rely
-	   on being able to manipulate the branch predictor for a victim
-	   context by executing aliasing branches in the attacker context.
-	   Such attacks can be partially mitigated against by clearing
-	   internal branch predictor state and limiting the prediction
-	   logic in some situations.
+	  Speculation attacks against some high-performance processors rely
+	  on being able to manipulate the branch predictor for a victim
+	  context by executing aliasing branches in the attacker context.
+	  Such attacks can be partially mitigated against by clearing
+	  internal branch predictor state and limiting the prediction
+	  logic in some situations.
 
-	   This config option will take CPU-specific actions to harden
-	   the branch predictor against aliasing attacks and may rely on
-	   specific instruction sequences or control bits being set by
-	   the system firmware.
+	  This config option will take CPU-specific actions to harden
+	  the branch predictor against aliasing attacks and may rely on
+	  specific instruction sequences or control bits being set by
+	  the system firmware.
 
-	   If unsure, say Y.
+	  If unsure, say Y.
 
 config HARDEN_BRANCH_HISTORY
 	bool "Harden Spectre style attacks against branch history" if EXPERT
@@ -1005,14 +1005,14 @@ if CACHE_L2X0
 config PL310_ERRATA_588369
 	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
 	help
-	   The PL310 L2 cache controller implements three types of Clean &
-	   Invalidate maintenance operations: by Physical Address
-	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
-	   They are architecturally defined to behave as the execution of a
-	   clean operation followed immediately by an invalidate operation,
-	   both performing to the same memory location. This functionality
-	   is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
-	   as clean lines are not invalidated as a result of these operations.
+	  The PL310 L2 cache controller implements three types of Clean &
+	  Invalidate maintenance operations: by Physical Address
+	  (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+	  They are architecturally defined to behave as the execution of a
+	  clean operation followed immediately by an invalidate operation,
+	  both performing to the same memory location. This functionality
+	  is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
+	  as clean lines are not invalidated as a result of these operations.
 
 config PL310_ERRATA_727915
 	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
-- 
2.32.0