[PATCH v2 4/6] arm64/sysreg: Generate definitions for CSSELR_EL1
Mark Brown
broonie at kernel.org
Fri May 20 09:16:36 PDT 2022
Convert CSSELR_EL1 to automatic generation as per DDI0487H.a, no functional
change.
Signed-off-by: Mark Brown <broonie at kernel.org>
Reviewed-by: Mark Rutland <mark.rutland at arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 7 +++++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7603c3344697..d1ca7f11e110 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -462,8 +462,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
-
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4bf413770b65..759075747dcc 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -262,6 +262,13 @@ Res0 14:12
Field 11:0 AFFINITY
EndSysreg
+Sysreg CSSELR_EL1 3 2 0 0 0
+Res0 63:5
+Field 4 TnD
+Field 3:1 Level
+Field 0 InD
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
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