[PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0

[Mark Rutland]

On Tue, May 17, 2022 at 07:22:18PM +0100, Mark Brown wrote:
> Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no
> functional change.
> 
> Signed-off-by: Mark Brown <broonie at kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 2 --
>  arch/arm64/tools/sysreg         | 6 ++++++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e8e9040227f6..09dc437030f5 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,8 +461,6 @@
>  #define SMIDR_EL1_SMPS_SHIFT	15
>  #define SMIDR_EL1_AFFINITY_SHIFT	0
>  
> -#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
> -
>  #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
>  #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
>  
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 543ba10f3dac..1cd1e4ea42e3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -292,6 +292,12 @@ Res0	13:4
>  Field	3:0	IminLine
>  EndSysreg
>  
> +Sysreg	DCZID_EL0	3	3	0	0	7
> +Res0	63:5
> +Field	4	DZP
> +Field	3:0	BS
> +EndSysreg

These all look correct to me per ARM DDI 0487H.a pages D13-5340 to D13-5341.

However, we have existing DCZID_DZP_SHIFT and DCZID_BS_SHIFT definitions that
should be converted over:

arch/arm64/include/asm/sysreg.h:#define DCZID_DZP_SHIFT                 4
arch/arm64/include/asm/sysreg.h:#define DCZID_BS_SHIFT                  0
arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),

Mark.

> +
>  Sysreg	SVCR	3	3	4	2	2
>  Res0	63:2
>  Field	1	ZA
> -- 
> 2.30.2
>