[PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0

[Mark Rutland]

On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote:
> Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
> functional change.
> 
> Signed-off-by: Mark Brown <broonie at kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  1 -
>  arch/arm64/tools/sysreg         | 15 +++++++++++++++
>  2 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6240149f9818..c77e2310d189 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,7 +461,6 @@
>  #define SMIDR_EL1_SMPS_SHIFT	15
>  #define SMIDR_EL1_AFFINITY_SHIFT	0
>  
> -#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
>  #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
>  
>  #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 47c4c45d5dc3..3971e1fb6af4 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -277,6 +277,21 @@ Field	3:1	Level
>  Field	0	InD
>  EndSysreg
>  
> +Sysreg	CTR_EL0	3	3	0	0	1
> +Res0	63:38
> +Field	37:32	TminLine
> +Res1	31
> +Res0	30
> +Field	29	DIC
> +Field	28	IDC
> +Field	27:24	CWG
> +Field	23:20	ERG
> +Field	19:16	DminLine
> +Field	15:14	L1Ip
> +Res0	13:4
> +Field	3:0	IminLine
> +EndSysreg

The values all look right to me.

The L1Ip field is an enumeration where:

* 0b00 means VPIPT
* 0b01 means AIVIVT // reserved in ARMv8
* 0b10 means VIPT
* 0b11 means PIPT

So I reckon we want to describe that as:

Enum	15:14	L1Ip
	0b00	VPIPT
	0b01	AIVIVT	# or RESERVED
	0b10	VIPT
	0b11	PIPT
EndEnum

We have some existing definitions that could be removed (and their users
converted over):

| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT      0
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED   1
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT       2
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT       3

Thanks,
Mark.

> +
>  Sysreg	SVCR	3	3	4	2	2
>  Res0	63:2
>  Field	1	ZA
> -- 
> 2.30.2
>