[PATCH v7 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers

[Nícolas F. R. A. Prado]

Hi Rex,

On Thu, May 19, 2022 at 08:55:15PM +0800, Rex-BC Chen wrote:
> The bank offsets are not serial for all reset registers.
> For example, there are five infra reset banks for MT8192: 0x120, 0x130,
> 0x140, 0x150 and 0x730.
> 
> To support this,
> - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
>   the reset register.
> - Add a new define RST_NR_PER_BANK to define reset number for each
>   reset bank.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---

<snip>

> diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
> index 9cfd589939e5..5cbc5c42204d 100644
> --- a/drivers/clk/mediatek/clk-mt2701-g3d.c
> +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
> @@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
>  	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
>  };
>  
> +static u16 rst_ofs[] = { 0xC, };

Very nitpicky, but you could have left the hex lowercase '0xc'.

Thanks,
Nícolas