[PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx

[Mark Rutland]

On Tue, May 17, 2022 at 07:22:14PM +0100, Mark Brown wrote:
> Convert the CPACR system register definitions to be automatically generated
> using the definitions in DDI0487H.a. The kernel does have some additional
> definitions for subfields of SMEN, FPEN and ZEN which are not identified as
> distinct subfields in the architecture so the definitions are not updated
> as part of this patch.

Maybe we should covert those over to an enumeration style?

> 
> No functional change.
> 
> Signed-off-by: Mark Brown <broonie at kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  2 --
>  arch/arm64/tools/sysreg         | 16 ++++++++++++++++
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 5a5d6bdaa806..c30f5aafde34 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -209,7 +209,6 @@
>  #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
>  
>  #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
> -#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
>  #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
>  #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
>  
> @@ -613,7 +612,6 @@
>  
>  /* VHE encodings for architectural EL0/1 system registers */
>  #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
> -#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)

The corresponding addition to the sysreg file got caught in the prior patch
(bad rebase?).

>  #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
>  #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
>  #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index e938d1117d36..21d5c140fde3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,22 @@ Field	1	A
>  Field	0	M
>  EndSysreg
>  
> +SysregFields	CPACR_ELx
> +Res0	63:29
> +Field	28	TTA
> +Res0	27:26
> +Field	25:24	SMEN
> +Res0	23:22
> +Field	21:20	FPEN
> +Res0	19:18
> +Field	17:16	ZEN
> +Res0	15:0
> +EndSysregFields
> +
> +Sysreg	CPACR_EL1	3	0	1	0	2
> +Fields	CPACR_ELx
> +EndSysreg

These all look right to me for CPACR_EL1.

Thanks,
Mark.

> +
>  Sysreg	SMPRI_EL1	3	0	1	2	4
>  Res0	63:4
>  Field	3:0	PRIORITY
> -- 
> 2.30.2
>