[PATCH] clk: mediatek: Fix unused 'ops' field in mtk_pll_data

[AngeloGioacchino Del Regno]

Il 19/05/22 21:27, Boris Lysov ha scritto:
> Hello, Angelo!
> 
> On Wed, 18 May 2022 14:15:13 +0200
> AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com> wrote:
> 
>> Il 15/05/22 14:24, Boris Lysov ha scritto:
>>> From: Boris Lysov <arzamas-16 at mail.ee>
>>>
>>> Allow to specify optional clk_ops in mtk_pll_data which will be picked up in
>>> mtk_clk_register_pll. So far no already supported Mediatek SoC needs
>>> non-default clk_ops for PLLs but instead of removing this field it will be
>>> actually used in the future for supporting older SoCs (see [1] for details)
>>> with quirky PLLs.
>>>
>>
>> Hello Boris,
>>
>> I disagree about this change and would rather see the ops pointer removed
>> with fire.
>>
>> I got that you're trying to do something about "quirky PLLs", but is it
>> really about the PLLs that you're mentioning being "quirky", or are they
>> simply a different IP?
> 
> To be honest I don't know exactly. mt6577 seems to share some common IP
> patterns such as splitting the entire clock system into few smaller subsystems
> such as apmixed (PLLs), topckgen (mux control), infra- and pericfg (internal
> and peripheral gate control). On the other hand, mt6577 is quite an old SoC
> (more on that in the end) and there are some differences about its operation
> compared to modern SoCs and their drivers.
> 
>> Also, if it's just about a bit inversion and a bigger delay:
>> 1. Bigger delay: Depending on how bigger, we may simply delay more by default
>>      for all PLLs, even the ones that aren't requiring us to wait for longer...
>>      ...after all, if it's about waiting for 10/20 *microseconds* more
>> { snip }
> 
> According to the mt6577 datasheet the largest settling time is 10
> *milli*seconds for AUDPLL [1]. In my opinion this is way too much to be set as
> default for all mediatek devices.
> 

Wow. 10ms is a huge wait! That doesn't *feel* right, but if that's what it is...
Perhaps we should look into that AUDPLL matter later, as audio is one kind of
functionality that you want to enable in the immediate term - I agree it's a
nice to have, but bringing up the platform comes first, and this means the top
clock controllers and eventually multimedia (to get a display up!).

>> 2. Bit inversion: that can be solved simply with a flag in the
>> prepare/unprepare ops for this driver... and if you want something that
>> performs even better, sparing you a nanosecond or two, you can always assign
>> an "inverted" callback for managing that single bit;
> 
> Not all mt6577 PLLs need bit inversion. 2 PLLs follow the common flow (set a
> CON0_PWR_ON bit to start). 6 PLLs set this bit to 0 to start. And 1 PLL (which
> is actually a DDS) needs to write a magic value to specific register (in
> apmixed region) to start.

That's interesting.

> Is very unfortunate that I can't directly link the vomit-inducing downstream
> code to prove the PLL situation due to its licensing but it's publicly
> available on the internet [2] as a part of device manufacturers' obligations to
> publish source code.
> 
>> 3. Different IP: mtk_clk_register_(name-of-the-new-ip)_pll() - I don't think
>> that there's anything to explain to that one.
> In my opinion this would introduce more duplicate code than just letting a
> developer set custom clk_ops for a specific platform.
> 
> Huge thanks for your feedback!
> 
> P.S As I said above, mt6577 is old and in its current state [3] it's closer to
> being a personal project than a serious mainlining attempt. I share and agree
> with your opinion [4] on e-waste and is why I'm trying to put an effort into it.
> What I don't have enough of is time and, sadly, expertise. Maybe it'd be better
> for me to stay on github.
> 

Your contribution is definitely welcome and you shouldn't worry about having
a relatively low amount of time to spend on these things - that's a very common
(non)issue among contributors.

A community works like a community: it's not everything on your shoulders!
That's why the maintainers are here, that's why I'm here and that's also why
other people are here. Everyone of us gives some little bit and, at the end of
the day, all these little bits come together to form an entire kernel :-)

Therefore, I encourage you (and anyone else reading this) to keep sharing your
valuable contributions to the mailing lists as much as you want to.


That said, let's get back in topic, shall we?
I feel the various concerns that you've raised relative to this PLL matter, I
know that older MediaTek SoCs look a bit strange in regard to some clocks and
other things, but that obviously doesn't mean that there's no way to do things
properly or anyway in a way better manner.

Here's my proposal:
Try upstreaming the top, very necessary, clocks to achieve a full console boot,
as this gives you a good chance to start landing some solid and critical base
for your platform.

The top clocks should have most of the PLLs, but you can avoid adding some that
are a bit problematic, such as that AUDPLL that you were talking about... in my
opinion, at least, it's not a big deal if we add these PLLs later when enabling
more functionality: that will give you the chance to add the PLLs that are in
need of that "enable bit inversion" logic which, from what I understand from
your words, covers 6 to 8 PLLs. That's a lot, because that makes you able to
add all of the clocks that are in infra, top, mfg, apmixed: like that, you're
also getting most of the IP up (timers, i2c, spi, mtk-sd for your eMMC/uSD).

Do it step by step - me and other developers will give you reviews and probably
make you go through some iterations of your driver, and that's to make sure that
your contribution will be valuable for a long time (and will not get broken, and
will not be useless after few months).


Cheers,
Angelo