[PATCH v2 1/2] Documentation/barriers: Add memory barrier dma_mb()

[Kefeng Wang]

The memory barrier dma_mb() is introduced by commit a76a37777f2c
("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"),
which is used to ensure that prior (both reads and writes) accesses to
memory by a CPU are ordered w.r.t. a subsequent MMIO write.

Signed-off-by: Kefeng Wang <wangkefeng.wang at huawei.com>
---
 Documentation/memory-barriers.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index b12df9137e1c..1eabcc0e4eca 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -1894,10 +1894,13 @@ There are some more advanced barrier functions:
 
  (*) dma_wmb();
  (*) dma_rmb();
+ (*) dma_mb();
 
      These are for use with consistent memory to guarantee the ordering
      of writes or reads of shared memory accessible to both the CPU and a
-     DMA capable device.
+     DMA capable device, in the case of ensure the prior (both reads and
+     writes) accesses to memory by a CPU are ordered w.r.t. a subsequent
+     MMIO write, dma_mb().
 
      For example, consider a device driver that shares memory with a device
      and uses a descriptor status value to indicate if the descriptor belongs
-- 
2.35.3