[PATCH 6/6] arm64: tegra: Enable OPE on various platforms
Sameer Pujar
spujar at nvidia.com
Wed May 18 10:36:12 PDT 2022
Enable OPE module usage on various Jetson platforms. This can be plugged
into an audio path using ALSA mixer controls. Add audio-graph-port binding
to use OPE device with generic audio-graph based sound card.
Signed-off-by: Sameer Pujar <spujar at nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 43 +++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 43 +++++++++++
.../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 43 +++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 84 ++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 84 ++++++++++++++++++++++
.../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 43 +++++++++++
6 files changed, 340 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 70737a0..05543c3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -915,6 +915,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port at 70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif at 290f000 {
@@ -1911,6 +1927,31 @@
};
};
+ ope at 2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer at 290bb00 {
status = "okay";
@@ -2552,6 +2593,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2571,6 +2613,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* I/O */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 7df8983..151c3d2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -868,6 +868,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port at 70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif at 290f000 {
@@ -1710,6 +1726,31 @@
};
};
+ ope at 2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer at 290bb00 {
status = "okay";
@@ -2273,6 +2314,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2291,6 +2333,7 @@
<&mixer_out4_port>, <&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index 7acc32d..35c50fe 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -878,6 +878,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port at 70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif at 290f000 {
@@ -1770,6 +1786,31 @@
};
};
+ ope at 2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer at 290bb00 {
status = "okay";
@@ -2323,6 +2364,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2342,6 +2384,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s3_port>, <&i2s5_port>,
<&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 328fbfe..55dcbf6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -682,6 +682,56 @@
};
};
+ ope at 702d8000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
+ ope at 702d8400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_in_ep>;
+ };
+ };
+
+ ope2_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_out_ep>;
+ };
+ };
+ };
+ };
+
amixer at 702dbb00 {
status = "okay";
@@ -1251,6 +1301,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
+
+ xbar_ope1_in_port: port at 41 {
+ reg = <0x41>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 42 {
+ reg = <0x42>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
+
+ xbar_ope2_in_port: port at 43 {
+ reg = <0x43>;
+
+ xbar_ope2_in_ep: endpoint {
+ remote-endpoint = <&ope2_cif_in_ep>;
+ };
+ };
+
+ port at 44 {
+ reg = <0x44>;
+
+ xbar_ope2_out_ep: endpoint {
+ remote-endpoint = <&ope2_cif_out_ep>;
+ };
+ };
};
};
};
@@ -1281,6 +1363,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -1293,6 +1376,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
+ <&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 746bd52..1c6882d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -1074,6 +1074,56 @@
};
};
+ ope at 702d8000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
+ ope at 702d8400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_in_ep>;
+ };
+ };
+
+ ope2_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_out_ep>;
+ };
+ };
+ };
+ };
+
amixer at 702dbb00 {
status = "okay";
@@ -1611,6 +1661,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
+
+ xbar_ope1_in_port: port at 41 {
+ reg = <0x41>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 42 {
+ reg = <0x42>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
+
+ xbar_ope2_in_port: port at 43 {
+ reg = <0x43>;
+
+ xbar_ope2_in_ep: endpoint {
+ remote-endpoint = <&ope2_cif_in_ep>;
+ };
+ };
+
+ port at 44 {
+ reg = <0x44>;
+
+ xbar_ope2_out_ep: endpoint {
+ remote-endpoint = <&ope2_cif_out_ep>;
+ };
+ };
};
};
};
@@ -1884,6 +1966,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -1896,6 +1979,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
+ <&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index 14289f86..83c566c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -867,6 +867,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port at 70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port at 71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
i2s at 2901000 {
@@ -1490,6 +1506,31 @@
};
};
+ ope at 2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port at 1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
mvc at 290a000 {
status = "okay";
@@ -2045,6 +2086,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2063,6 +2105,7 @@
<&mix_out4_port>, <&mix_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
--
2.7.4
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