Panic in arch_hw_breakpoint_init() on Cortex-A9 (SPEAr1340)

[Arnd Bergmann]

On Wed, Apr 19, 2017 at 11:31 AM Mark Rutland <mark.rutland at arm.com> wrote:
> On Tue, Apr 18, 2017 at 07:11:21PM +0200, Lubomir Rintel wrote:
> > On Tue, 2017-04-18 at 14:03 +0100, Mark Rutland wrote:
> > > On Tue, Apr 18, 2017 at 12:44:28PM +0200, Lubomir Rintel wrote:
> > $ addr2line -ife vmlinux c0905504
> > core_has_os_save_restore
> > /home/lkundrak/spear/linux/arch/arm/kernel/hw_breakpoint.c:920
>
> That's a read of DBGOSLSR, which shouldn't UNDEF.
>
> I suspect this is a result of Cortex-A9 erratum 764319, which causes
> DBGOSLSR to unexpectedly behave as UNDEF when the external DBGSWENABLE
> pin is wired to 0.
>
> The official workaround is to ensure that the DBGSWENABLE pin is wired
> to 1.
>
> It might be possible to handle the trap and bail out, but it's not clear
> to me if we can safely assume that other functionality is available.

I searched for 764319 as Nick posted a patch for an errata workaround
recently. If this problem still exists on the SPEAr1340, maybe the
same patch will fix it. See [1] for the initial proposal that worked for
Nick. I think there is a better way to do it, but either way it should address
other platforms as well.

       Arnd

[1] https://lore.kernel.org/lkml/20220506192957.24889-1-nick.hawkins@hpe.com/