[xilinx-xlnx:xlnx_rebase_v5.15_LTS 629/1129] drivers/gpu/drm/xlnx/xlnx_dsi.c:88:33: warning: conversion from 'long long unsigned int' to 'long unsigned int' changes value from '200000000000' to '2431504384'
kernel test robot
lkp at intel.com
Sat May 7 13:04:01 PDT 2022
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.15_LTS
head: 3076249fc30bf463f8390f89009de928ad3e95ff
commit: 32f4c7d25b52562567b652709480223cf36e3229 [629/1129] drm: xlnx: dsi: Adding dsi driver to new framework
config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20220508/202205080308.C21wPAzl-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/Xilinx/linux-xlnx/commit/32f4c7d25b52562567b652709480223cf36e3229
git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xilinx-xlnx xlnx_rebase_v5.15_LTS
git checkout 32f4c7d25b52562567b652709480223cf36e3229
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash drivers/gpu/drm/xlnx/ drivers/media/platform/xilinx/ drivers/net/ethernet/xilinx/ drivers/phy/xilinx/ drivers/staging/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/xlnx/xlnx_dsi.c: In function 'xlnx_dsi_probe':
>> drivers/gpu/drm/xlnx/xlnx_dsi.c:88:33: warning: conversion from 'long long unsigned int' to 'long unsigned int' changes value from '200000000000' to '2431504384' [-Woverflow]
88 | #define XDSI_DPHY_CLK_REQ 200000000000UL
| ^~~~~~~~~~~~~~
drivers/gpu/drm/xlnx/xlnx_dsi.c:967:48: note: in expansion of macro 'XDSI_DPHY_CLK_REQ'
967 | ret = clk_set_rate(dsi->dphy_clk_200M, XDSI_DPHY_CLK_REQ);
| ^~~~~~~~~~~~~~~~~
vim +88 drivers/gpu/drm/xlnx/xlnx_dsi.c
85
86 #define XDSI_DPHY_CLK_MIN 197000000000UL
87 #define XDSI_DPHY_CLK_MAX 203000000000UL
> 88 #define XDSI_DPHY_CLK_REQ 200000000000UL
89
--
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https://01.org/lkp
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