[xilinx-xlnx:xlnx_rebase_v5.15_LTS 225/1129] drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:35:31: warning: cast to pointer from integer of different size
kernel test robot
lkp at intel.com
Fri May 6 16:12:09 PDT 2022
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.15_LTS
head: 3076249fc30bf463f8390f89009de928ad3e95ff
commit: ee94241b2118ddd38a456b2b805fc584b57de58f [225/1129] net: axienet: added multichannel DMA support
config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20220507/202205070717.SDe3HCh3-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/Xilinx/linux-xlnx/commit/ee94241b2118ddd38a456b2b805fc584b57de58f
git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xilinx-xlnx xlnx_rebase_v5.15_LTS
git checkout ee94241b2118ddd38a456b2b805fc584b57de58f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash drivers/clk/ drivers/gpu/drm/xlnx/ drivers/media/i2c/ drivers/media/mc/ drivers/media/platform/xilinx/ drivers/misc/ drivers/net/ethernet/xilinx/ drivers/phy/xilinx/ drivers/ptp/ drivers/staging/ drivers/uio/ drivers/usb/host/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:16:
drivers/net/ethernet/xilinx/xilinx_axienet.h: In function 'axienet_dma_bdout':
drivers/net/ethernet/xilinx/xilinx_axienet.h:973:9: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
973 | writeq(value, (q->dma_regs + reg));
| ^~~~~~
| writeb
In file included from include/net/net_namespace.h:39,
from include/linux/netdevice.h:37,
from drivers/net/ethernet/xilinx/xilinx_axienet.h:12,
from drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:16:
drivers/net/ethernet/xilinx/xilinx_axienet_dma.c: In function 'axienet_bd_free':
>> drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:35:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
35 | dev_kfree_skb((struct sk_buff *)
| ^
include/linux/skbuff.h:1211:45: note: in definition of macro 'dev_kfree_skb'
1211 | #define dev_kfree_skb(a) consume_skb(a)
| ^
drivers/net/ethernet/xilinx/xilinx_axienet_dma.c: In function '__dma_rxq_init':
>> drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:167:46: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
167 | q->rx_bd_v[i].sw_id_offset = (phys_addr_t)skb;
| ^
drivers/net/ethernet/xilinx/xilinx_axienet_dma.c: In function 'axienet_dma_err_handler':
drivers/net/ethernet/xilinx/xilinx_axienet_dma.c:412:43: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
412 | dev_kfree_skb_irq((struct sk_buff *)cur_p->tx_skb);
| ^
cc1: some warnings being treated as errors
--
In file included from drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c:23:
drivers/net/ethernet/xilinx/xilinx_axienet.h: In function 'axienet_dma_bdout':
drivers/net/ethernet/xilinx/xilinx_axienet.h:973:9: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
973 | writeq(value, (q->dma_regs + reg));
| ^~~~~~
| writeb
In file included from include/linux/netlink.h:7,
from include/linux/ethtool.h:18,
from include/linux/phy.h:16,
from include/linux/of_mdio.h:12,
from drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c:17:
drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c: In function 'axienet_mcdma_rx_bd_free':
>> drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c:143:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
143 | dev_kfree_skb((struct sk_buff *)
| ^
include/linux/skbuff.h:1211:45: note: in definition of macro 'dev_kfree_skb'
1211 | #define dev_kfree_skb(a) consume_skb(a)
| ^
drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c: In function 'axienet_mcdma_rx_q_init':
>> drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c:277:47: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
277 | q->rxq_bd_v[i].sw_id_offset = (phys_addr_t)skb;
| ^
drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c: In function 'axienet_mcdma_err_handler':
drivers/net/ethernet/xilinx/xilinx_axienet_mcdma.c:621:43: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
621 | dev_kfree_skb_irq((struct sk_buff *)cur_p->tx_skb);
| ^
cc1: some warnings being treated as errors
vim +35 drivers/net/ethernet/xilinx/xilinx_axienet_dma.c
2
3 /* Xilinx AXI Ethernet (DMA programming)
4 *
5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii at dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr at monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2010 - 2012 Xilinx, Inc.
11 * Copyright (C) 2018 Xilinx, Inc. All rights reserved.
12 *
13 * This file contains helper functions for AXI DMA TX and RX programming.
14 */
15
> 16 #include "xilinx_axienet.h"
17
18 /**
19 * axienet_bd_free - Release buffer descriptor rings for individual dma queue
20 * @ndev: Pointer to the net_device structure
21 * @q: Pointer to DMA queue structure
22 *
23 * This function is helper function to axienet_dma_bd_release.
24 */
25
26 void __maybe_unused axienet_bd_free(struct net_device *ndev,
27 struct axienet_dma_q *q)
28 {
29 int i;
30 struct axienet_local *lp = netdev_priv(ndev);
31
32 for (i = 0; i < lp->rx_bd_num; i++) {
33 dma_unmap_single(ndev->dev.parent, q->rx_bd_v[i].phys,
34 lp->max_frm_size, DMA_FROM_DEVICE);
> 35 dev_kfree_skb((struct sk_buff *)
36 (q->rx_bd_v[i].sw_id_offset));
37 }
38
39 if (q->rx_bd_v) {
40 dma_free_coherent(ndev->dev.parent,
41 sizeof(*q->rx_bd_v) * lp->rx_bd_num,
42 q->rx_bd_v,
43 q->rx_bd_p);
44 }
45 if (q->tx_bd_v) {
46 dma_free_coherent(ndev->dev.parent,
47 sizeof(*q->tx_bd_v) * lp->tx_bd_num,
48 q->tx_bd_v,
49 q->tx_bd_p);
50 }
51 if (q->tx_bufs) {
52 dma_free_coherent(ndev->dev.parent,
53 XAE_MAX_PKT_LEN * lp->tx_bd_num,
54 q->tx_bufs,
55 q->tx_bufs_dma);
56 }
57 }
58
59 /**
60 * __dma_txq_init - Setup buffer descriptor rings for individual Axi DMA-Tx
61 * @ndev: Pointer to the net_device structure
62 * @q: Pointer to DMA queue structure
63 *
64 * Return: 0, on success -ENOMEM, on failure
65 *
66 * This function is helper function to axienet_dma_q_init
67 */
68 static int __dma_txq_init(struct net_device *ndev, struct axienet_dma_q *q)
69 {
70 int i;
71 u32 cr;
72 struct axienet_local *lp = netdev_priv(ndev);
73
74 q->tx_bd_ci = 0;
75 q->tx_bd_tail = 0;
76
77 q->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
78 sizeof(*q->tx_bd_v) * lp->tx_bd_num,
79 &q->tx_bd_p, GFP_KERNEL);
80 if (!q->tx_bd_v)
81 goto out;
82
83 for (i = 0; i < lp->tx_bd_num; i++) {
84 q->tx_bd_v[i].next = q->tx_bd_p +
85 sizeof(*q->tx_bd_v) *
86 ((i + 1) % lp->tx_bd_num);
87 }
88
89 if (!q->eth_hasdre) {
90 q->tx_bufs = dma_alloc_coherent(ndev->dev.parent,
91 XAE_MAX_PKT_LEN * lp->tx_bd_num,
92 &q->tx_bufs_dma,
93 GFP_KERNEL);
94 if (!q->tx_bufs)
95 goto out;
96
97 for (i = 0; i < lp->tx_bd_num; i++)
98 q->tx_buf[i] = &q->tx_bufs[i * XAE_MAX_PKT_LEN];
99 }
100
101 /* Start updating the Tx channel control register */
102 cr = axienet_dma_in32(q, XAXIDMA_TX_CR_OFFSET);
103 /* Update the interrupt coalesce count */
104 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
105 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
106 /* Update the delay timer count */
107 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
108 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
109 /* Enable coalesce, delay timer and error interrupts */
110 cr |= XAXIDMA_IRQ_ALL_MASK;
111 /* Write to the Tx channel control register */
112 axienet_dma_out32(q, XAXIDMA_TX_CR_OFFSET, cr);
113
114 /* Write to the RS (Run-stop) bit in the Tx channel control register.
115 * Tx channel is now ready to run. But only after we write to the
116 * tail pointer register that the Tx channel will start transmitting.
117 */
118 axienet_dma_bdout(q, XAXIDMA_TX_CDESC_OFFSET, q->tx_bd_p);
119 cr = axienet_dma_in32(q, XAXIDMA_TX_CR_OFFSET);
120 axienet_dma_out32(q, XAXIDMA_TX_CR_OFFSET,
121 cr | XAXIDMA_CR_RUNSTOP_MASK);
122 return 0;
123 out:
124 return -ENOMEM;
125 }
126
127 /**
128 * __dma_rxq_init - Setup buffer descriptor rings for individual Axi DMA-Rx
129 * @ndev: Pointer to the net_device structure
130 * @q: Pointer to DMA queue structure
131 *
132 * Return: 0, on success -ENOMEM, on failure
133 *
134 * This function is helper function to axienet_dma_q_init
135 */
136 static int __dma_rxq_init(struct net_device *ndev,
137 struct axienet_dma_q *q)
138 {
139 int i;
140 u32 cr;
141 struct sk_buff *skb;
142 struct axienet_local *lp = netdev_priv(ndev);
143 /* Reset the indexes which are used for accessing the BDs */
144 q->rx_bd_ci = 0;
145
146 /* Allocate the Rx buffer descriptors. */
147 q->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
148 sizeof(*q->rx_bd_v) * lp->rx_bd_num,
149 &q->rx_bd_p, GFP_KERNEL);
150 if (!q->rx_bd_v)
151 goto out;
152
153 for (i = 0; i < lp->rx_bd_num; i++) {
154 q->rx_bd_v[i].next = q->rx_bd_p +
155 sizeof(*q->rx_bd_v) *
156 ((i + 1) % lp->rx_bd_num);
157
158 skb = netdev_alloc_skb(ndev, lp->max_frm_size);
159 if (!skb)
160 goto out;
161
162 /* Ensure that the skb is completely updated
163 * prio to mapping the DMA
164 */
165 wmb();
166
> 167 q->rx_bd_v[i].sw_id_offset = (phys_addr_t)skb;
168 q->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
169 skb->data,
170 lp->max_frm_size,
171 DMA_FROM_DEVICE);
172 q->rx_bd_v[i].cntrl = lp->max_frm_size;
173 }
174
175 /* Start updating the Rx channel control register */
176 cr = axienet_dma_in32(q, XAXIDMA_RX_CR_OFFSET);
177 /* Update the interrupt coalesce count */
178 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
179 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
180 /* Update the delay timer count */
181 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
182 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
183 /* Enable coalesce, delay timer and error interrupts */
184 cr |= XAXIDMA_IRQ_ALL_MASK;
185 /* Write to the Rx channel control register */
186 axienet_dma_out32(q, XAXIDMA_RX_CR_OFFSET, cr);
187
188 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
189 * halted state. This will make the Rx side ready for reception.
190 */
191 axienet_dma_bdout(q, XAXIDMA_RX_CDESC_OFFSET, q->rx_bd_p);
192 cr = axienet_dma_in32(q, XAXIDMA_RX_CR_OFFSET);
193 axienet_dma_out32(q, XAXIDMA_RX_CR_OFFSET,
194 cr | XAXIDMA_CR_RUNSTOP_MASK);
195 axienet_dma_bdout(q, XAXIDMA_RX_TDESC_OFFSET, q->rx_bd_p +
196 (sizeof(*q->rx_bd_v) * (lp->rx_bd_num - 1)));
197
198 return 0;
199 out:
200 return -ENOMEM;
201 }
202
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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