[RFC PATCH v2 3/3] arm64: implement dynamic shadow call stack for Clang
Nick Desaulniers
ndesaulniers at google.com
Thu May 5 14:01:43 PDT 2022
On Thu, May 5, 2022 at 9:10 AM Ard Biesheuvel <ardb at kernel.org> wrote:
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index b6302f7cd73f..df7a7aff456a 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -357,6 +357,14 @@ config KASAN_SHADOW_OFFSET
> config UNWIND_TABLES
> bool
>
> +config UNWIND_PATCH_PAC_INTO_SCS
> + def_bool y
> + depends on CC_IS_CLANG && CLANG_VERSION >= 150000
Consider adding a comment that links to the corresponding GCC bug
report, which can be replaced with a version check once fixed.
> + depends on SHADOW_CALL_STACK
> + depends on ARM64_PTR_AUTH_KERNEL
> + select UNWIND_TABLES
> + select DYNAMIC_SCS
> +
> source "arch/arm64/Kconfig.platforms"
>
> menu "Kernel Features"
> diff --git a/arch/arm64/kernel/patch-scs.c b/arch/arm64/kernel/patch-scs.c
> new file mode 100644
> index 000000000000..8c534630c2a1
> --- /dev/null
> +++ b/arch/arm64/kernel/patch-scs.c
> @@ -0,0 +1,257 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 - Google LLC
> + * Author: Ard Biesheuvel <ardb at google.com>
> + */
> +
> +#include <linux/bug.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/linkage.h>
> +#include <linux/printk.h>
> +#include <linux/types.h>
> +
> +#include <asm/cpufeature.h>
> +
> +#define DW_CFA_nop 0x00
> +#define DW_CFA_set_loc 0x01
> +#define DW_CFA_advance_loc1 0x02
> +#define DW_CFA_advance_loc2 0x03
> +#define DW_CFA_advance_loc4 0x04
> +#define DW_CFA_offset_extended 0x05
> +#define DW_CFA_restore_extended 0x06
> +#define DW_CFA_undefined 0x07
> +#define DW_CFA_same_value 0x08
> +#define DW_CFA_register 0x09
> +#define DW_CFA_remember_state 0x0a
> +#define DW_CFA_restore_state 0x0b
> +#define DW_CFA_def_cfa 0x0c
> +#define DW_CFA_def_cfa_register 0x0d
> +#define DW_CFA_def_cfa_offset 0x0e
> +#define DW_CFA_def_cfa_expression 0x0f
> +#define DW_CFA_expression 0x10
> +#define DW_CFA_offset_extended_sf 0x11
> +#define DW_CFA_def_cfa_sf 0x12
> +#define DW_CFA_def_cfa_offset_sf 0x13
> +#define DW_CFA_val_offset 0x14
> +#define DW_CFA_val_offset_sf 0x15
> +#define DW_CFA_val_expression 0x16
> +#define DW_CFA_lo_user 0x1c
> +#define DW_CFA_negate_ra_state 0x2d
> +#define DW_CFA_GNU_args_size 0x2e
> +#define DW_CFA_GNU_negative_offset_extended 0x2f
> +#define DW_CFA_hi_user 0x3f
Might be more reusable to put these in their own header. Though, this
is currently the only user, so perhaps "YAGNI."
If there's some documentation to these values, consider adding a
comment with a link.
> +
> +extern const u8 __eh_frame_start[], __eh_frame_end[];
> +
> +struct fde_frame {
> + s32 initial_loc;
> + s32 range;
> +};
> +
> +enum {
> + PACIASP = 0xd503233f,
> + AUTIASP = 0xd50323bf,
> + SCS_PUSH = 0xf800865e,
> + SCS_POP = 0xf85f8e5e,
> +};
Is there anything we can reuse from arch/arm64/include/asm/insn.h
rather than hardcoding these values?
> +
> +static void __always_inline scs_patch_loc(u64 loc)
> +{
> + u32 insn = le32_to_cpup((void *)loc);
> +
> + switch (insn) {
> + case PACIASP:
> + *(u32 *)loc = cpu_to_le32(SCS_PUSH);
> + break;
> + case AUTIASP:
> + *(u32 *)loc = cpu_to_le32(SCS_POP);
> + break;
> + default:
> + /*
> + * While the DW_CFA_negate_ra_state directive is guaranteed to
> + * appear right after a PACIASP/AUTIASP instruction, it may
> + * also appear after a DW_CFA_restore_state directive that
> + * restores a state that is only partially accurate, and is
> + * followed by DW_CFA_negate_ra_state directive to toggle the
> + * PAC bit again. So we permit other instructions here, and ignore
> + * them.
> + */
> + break;
> + }
> +}
> +
> +/*
> + * Skip one uleb128/sleb128 encoded quantity from the opcode stream. All bytes
> + * except the last one have bit #7 set.
Consider using the BIT macro to express that.
> + */
> +static int __always_inline skip_xleb128(const u8 **opcode, int size)
> +{
> + u8 c;
> +
> + do {
> + c = *(*opcode)++;
> + size--;
> + } while (c & 0x80);
> +
> + return size;
> +}
> +
> +static int noinstr scs_handle_frame(const u8 eh_frame[], u32 size)
> +{
> + const struct fde_frame *fde;
> + const u8 *opcode;
> + u64 loc;
> +
> + /*
> + * For patching PAC opcodes, we only care about the FDE records, and
> + * not the CIE, which carries the initial CFA directives but they only
> + * pertain to which register is the stack pointer.
> + * TODO this is not 100% true - we need the augmentation string and the
> + * encoding but they are always the same in practice.
> + */
> + if (*(u32 *)eh_frame == 0)
> + return 0;
> +
> + fde = (const struct fde_frame *)(eh_frame + 4);
> + loc = (u64)offset_to_ptr(&fde->initial_loc);
> + opcode = (const u8 *)(fde + 1);
> +
> + // TODO check augmentation data
> + WARN_ON(*opcode++);
> + size -= sizeof(u32) + sizeof(*fde) + 1;
> +
> + /*
> + * Starting from 'loc', apply the CFA opcodes that advance the location
> + * pointer, and identify the locations of the PAC instructions.
> + */
> + do {
> + switch (*opcode & 0xC0) {
> + case 0:
> + // handle DW_CFA_xxx opcodes
> + switch (*opcode) {
> + case DW_CFA_nop:
> + case DW_CFA_remember_state:
> + case DW_CFA_restore_state:
> + break;
> +
> + case DW_CFA_advance_loc1:
> + loc += *++opcode;
> + size--;
> + break;
> +
> + case DW_CFA_advance_loc2:
> + loc += *++opcode;
> + loc += *++opcode << 8;
> + size -= 2;
> + break;
> +
> + case DW_CFA_def_cfa:
> + opcode++;
> + size = skip_xleb128(&opcode, --size);
> + size = skip_xleb128(&opcode, size);
> + continue;
> + case DW_CFA_def_cfa_offset:
> + case DW_CFA_def_cfa_offset_sf:
> + case DW_CFA_def_cfa_register:
> + case DW_CFA_same_value:
> + opcode++;
> + size = skip_xleb128(&opcode, --size);
> + continue;
> +
> + case DW_CFA_negate_ra_state:
> + scs_patch_loc(loc - 4);
> + break;
> +
> + default:
> + pr_err("unhandled opcode: %02x in FDE frame %lx\n", *opcode, (uintptr_t)eh_frame);
I'm curious, if we made these identifiers enum values, then we could
get coverage from -Wswitch.
Though then there is perhaps a risk that new values do start getting
produced by toolchains, and we'd miss adding the enum values in those
cases.
These nested switch statements make it hard to tell which values are
handled where without doing some arithmetic. Would one level of switch
statements with more cases be more readable? Or is there a goal to
have a smaller initial-level switch table?
> + return -ENOEXEC;
> + }
> + opcode++;
> + size--;
> + break;
> +
> + case 0x40:
> + // advance loc
> + loc += *opcode++ & 0x3f;
> + size--;
> + break;
> +
> + case 0x80:
> + opcode++;
> + size = skip_xleb128(&opcode, --size);
> + continue;
> +
> + default:
> + // ignore
> + opcode++;
> + size--;
> + break;
> + }
> + } while (size > 0);
> +
> + return 0;
> +}
> +
> +int noinstr scs_patch(const u8 eh_frame[], int size)
> +{
> + const u8 *p = eh_frame;
> +
> + while (size > 4) {
> + const u32 *frame_size = (const u32 *)p;
> + int ret;
> +
> + if (*frame_size != -1 && *frame_size <= size) {
> + ret = scs_handle_frame(p + 4, *frame_size);
> + if (ret)
> + return ret;
> + p += 4 + *frame_size;
> + size -= 4 + *frame_size;
> + }
> + }
> + return 0;
> +}
> +
> +extern struct arm64_ftr_override id_aa64isar1_override;
> +extern struct arm64_ftr_override id_aa64isar2_override;
> +extern struct arm64_ftr_override id_aa64pfr1_override;
Are these linker defined symbols, like __eh_frame_start/__eh_frame_end?
--
Thanks,
~Nick Desaulniers
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