Should arm64 have a custom crash shutdown handler?

[Mark Rutland]

On Wed, May 04, 2022 at 05:00:42PM -0300, Guilherme G. Piccoli wrote:
> Hi folks, this email is to ask feedback / trigger a discussion about the
> concept of custom crash shutdown handler, that is "missing" in arm64
> while it's present in many architectures [mips, powerpc, x86, sh (!)].
> 
> Currently, when we kexec in arm64, the function machine_crash_shutdown()
> is called as a handler to disable CPUs and (potentially) do extra
> quiesce work. In the aforementioned architectures, there's a way to
> override this function, if for example an hypervisor wish to have its
> guests running their own custom shutdown machinery.

What exactly do you need to do in this custom shutdown machinery?

The general expectation for arm64 is that any hypervisor can implement PSCI,
and as long as you have that, CPUs (and the VM as a whole) can be shutdown in a
standard way.

I suspect what you're actually after is a mechanism to notify the hypervisor
when the guest crashes, rather than changing the way the shutdown itself
occurs? If so, we already have panic notifiers, and QEMU has a "pvpanic"
device using that. See drivers/misc/pvpanic/.

Thanks,
Mark.

> For powerpc/mips, the approach is a generic shutdown function that might
> call other handler-registered functions, whereas x86/sh relies in the
> "machine_ops" structure, having the crash shutdown as a callback in such
> struct.
> 
> The usage for that is very broad, but heavy users are hypervisors like
> Hyper-V / KVM (CCed Michael and Vitaly here for this reason). The
> discussion about the need for that in arm64 is from another thread [0],
> so before start implementing/playing with that, I'd like to ask ARM64
> community if there is any feedback and in case it's positive, what is
> the best implementation strategy (struct callback vs. handler call), etc.
> 
> I've CCed ARM64/ARM32 maintainers plus extra people I found as really
> involved with ARM architecture - sorry if I added people I shouldn't or
> if I forgot somebody (though the ARM mailing-list is CC).
> Cheers,
> 
> 
> Guilherme
> 
> 
> [0]
> https://lore.kernel.org/lkml/2787b476-6366-1c83-db80-0393da417497@igalia.com/
> See the proposed option (b)