[PATCH v5 5/8] crypto: arm64/aes-xctr: Add accelerated implementation of XCTR

[Eric Biggers]

On Wed, Apr 27, 2022 at 12:37:56AM +0000, Nathan Huckleberry wrote:
> diff --git a/arch/arm64/crypto/aes-modes.S b/arch/arm64/crypto/aes-modes.S
> index dc35eb0245c5..39a0c2b5c24d 100644
> --- a/arch/arm64/crypto/aes-modes.S
> +++ b/arch/arm64/crypto/aes-modes.S
> @@ -318,126 +318,186 @@ AES_FUNC_END(aes_cbc_cts_decrypt)
>  	.byte		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
>  	.previous
>  
> -
>  	/*
> -	 * aes_ctr_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
> -	 *		   int bytes, u8 ctr[])
> +	 * This macro generates the code for CTR and XCTR mode.
>  	 */

So I did ask for the register aliases and extra comments, but it's hard to
review this with the cleanups to the existing code mixed in with the
XCTR-specific additions.  Would you mind splitting this up into two patches, one
to improve the readability of the existing aes_ctr_encrypt(), and one to add
xctr support?

Also, I noticed that the register aliases aren't being used consistently.  E.g.

	 ld1             {vctr.16b}, [x5]

... should use IV for x5, and

	eor             x6, x6, x12
	eor             x7, x7, x12
	eor             x8, x8, x12
	eor             x9, x9, x12
	eor             x10, x10, x12

Should use IV_PART for x12.

- Eric