[PATCH 4/6] ARM: spectre-bhb: use local DSB and elide ISB in loop8 sequence
Ard Biesheuvel
ardb at kernel.org
Mon Mar 28 06:47:12 PDT 2022
The loop8 mitigation for Spectre-BHB only requires a CPU local DSB
rather than a systemwide one, which is much more costly. And by the same
reasoning as why it is justified to omit the ISB after BPIALL, we can
also elide the ISB and rely on the exception return for the context
synchronization.
Signed-off-by: Ard Biesheuvel <ardb at kernel.org>
---
arch/arm/kernel/entry-armv.S | 5 +++--
arch/arm/kernel/entry-common.S | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index a5725e82addc..3a62ee790b5e 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -1049,8 +1049,9 @@ vector_bhb_loop8_\name:
3: W(b) . + 4
subs r0, r0, #1
bne 3b
- dsb
- isb
+ dsb nsh
+ @ isb not needed due to "movs pc, lr" in the vector stub
+ @ which gives a "context synchronisation".
b 2b
ENDPROC(vector_bhb_loop8_\name)
.previous
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index dbc1913ee30b..96016a5ad72f 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -162,7 +162,7 @@ ENTRY(vector_bhb_loop8_swi)
1: b 2f
2: subs r8, r8, #1
bne 1b
- dsb
+ dsb nsh
isb
b 3f
ENDPROC(vector_bhb_loop8_swi)
--
2.30.2
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