[PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
> 
> please see my comment below.
> 
> On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > Add display nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng at mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno at collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111
> > +++++++++++++++++++++++
> >  1 file changed, 111 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a77d405dd508..59183fb6c80b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1205,6 +1205,13 @@
> >  			#clock-cells = <1>;
> >  		};
> >  
> > +		mutex: mutex at 14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +		};
> > +
> >  		smi_common: smi at 14002000 {
> >  			compatible = "mediatek,mt8192-smi-common";
> >  			reg = <0 0x14002000 0 0x1000>;
> > @@ -1236,6 +1243,110 @@
> >  			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >  		};
> >  
> > +		ovl0: ovl at 14005000 {
> > +			compatible = "mediatek,mt8192-disp-ovl";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		ovl_2l0: ovl at 14006000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +		};
> > +
> > +		rdma0: rdma at 14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> > +			mediatek,rdma-fifo-size = <5120>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		color0: color at 14009000 {
> > +			compatible = "mediatek,mt8192-disp-color",
> > +				     "mediatek,mt8173-disp-color";
> > +			reg = <0 0x14009000 0 0x1000>;
> > +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +		};
> > +
> > +		ccorr0: ccorr at 1400a000 {
> > +			compatible = "mediatek,mt8192-disp-ccorr";
> > +			reg = <0 0x1400a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +		};
> > +
> > +		aal0: aal at 1400b000 {
> > +			compatible = "mediatek,mt8192-disp-aal",
> > +				     "mediatek,mt8193-disp-aal";
> 
> Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> aal", otherwise 
> the drm driver doesn't even probe. Typos happen, just please make
> sure you're
> testing before sending to the list so these kind of issues can be
> caught
> earlier.
> 
> Thanks,
> Nícolas
> 
Hi Nícolas,

Thanks for your kindly reminder.

There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
(mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)

In 8192, We should use mediatek,mt8183-disp-aal because of design.

Do I need to add some information for this in mediatek,disp.txt?

Best regards,
Allen

> > +			reg = <0 0x1400b000 0 0x1000>;
> > +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +		};