[PATCH 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}

[Marc Zyngier]

On Tue, 15 Mar 2022 23:16:05 +0000,
Oliver Upton <oupton at google.com> wrote:
> 
> Hi Marc,
> 
> On Mon, Mar 14, 2022 at 04:40:41PM +0000, Marc Zyngier wrote:
> > As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
> > the include file with the architectural values.
> > 
> > Signed-off-by: Marc Zyngier <maz at kernel.org>
> > ---
> >  include/linux/irqchip/arm-gic-v3.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> > index 12d91f0dedf9..aeb8ced53880 100644
> > --- a/include/linux/irqchip/arm-gic-v3.h
> > +++ b/include/linux/irqchip/arm-gic-v3.h
> > @@ -127,6 +127,8 @@
> >  #define GICR_PIDR2			GICD_PIDR2
> >  
> >  #define GICR_CTLR_ENABLE_LPIS		(1UL << 0)
> > +#define GICR_CTLR_IR			(1UL << 1)
> > +#define GICR_CTLR_CES			(1UL << 2)
> 
> I think these are backwards (IR is bit 2)

How embarrassing... The whole thing only works because we always
advertise the two bits together, and that the GIC driver has the same
bug. Fortunately, I'm running low on paper bags... ;-)

I'll push a fix for that shortly.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.