[PATCH 02/14] ARM: dts: suniv: F1C100: fix watchdog compatible

[Guenter Roeck]

On Mon, Mar 07, 2022 at 02:34:09PM +0000, Andre Przywara wrote:
> The F1C100 series of SoCs actually have their watchdog IP being
> compatible with the newer Allwinner generation, not the older one.
> 
> The currently described sun4i-a10-wdt actually does not work, neither
> the watchdog functionality (just never fires), nor the reset part
> (reboot hangs).
> 
> Replace the compatible string with the one used by the newer generation.
> Verified to work with both the watchdog and reboot functionality on a
> LicheePi Nano.
> 
> Also add the missing interrupt line and clock source, to make it binding
> compliant.
> 
> Fixes: 4ba16d17efdd ("ARM: dts: suniv: add initial DTSI file for F1C100s")
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>

Acked-by: Guenter Roeck <linux at roeck-us.net>

> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 6100d3b75f61..def830101448 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -104,8 +104,10 @@ timer at 1c20c00 {
>  
>  		wdt: watchdog at 1c20ca0 {
>  			compatible = "allwinner,suniv-f1c100s-wdt",
> -				     "allwinner,sun4i-a10-wdt";
> +				     "allwinner,sun6i-a31-wdt";
>  			reg = <0x01c20ca0 0x20>;
> +			interrupts = <16>;
> +			clocks = <&osc32k>;
>  		};
>  
>  		uart0: serial at 1c25000 {