[xilinx-xlnx:master 173/592] drivers/clk/clk-xlnx-clock-wizard.c:324:8: error: implicit declaration of function 'FIELD_PREP'

[kernel test robot]

Hi Shubhrajyoti,

FYI, the error/warning still remains.

tree:   https://github.com/Xilinx/linux-xlnx master
head:   ef4ac9cad9406e869e7c20191f3a3b0bb9663d81
commit: bf7387ee9a75c2a390b19f63c47076344e664b86 [173/592] clocking-wizard: Support higher frequency accuracy
config: arm-randconfig-r035-20220309 (https://download.01.org/0day-ci/archive/20220310/202203100259.o3TUVa5w-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 276ca87382b8f16a65bddac700202924228982f6)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # https://github.com/Xilinx/linux-xlnx/commit/bf7387ee9a75c2a390b19f63c47076344e664b86
        git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
        git fetch --no-tags xilinx-xlnx master
        git checkout bf7387ee9a75c2a390b19f63c47076344e664b86
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All errors (new ones prefixed by >>):

>> drivers/clk/clk-xlnx-clock-wizard.c:324:8: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
           reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |
                 ^
>> drivers/clk/clk-xlnx-clock-wizard.c:392:6: error: implicit declaration of function 'FIELD_GET' [-Werror,-Wimplicit-function-declaration]
           d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
               ^
   2 errors generated.


vim +/FIELD_PREP +324 drivers/clk/clk-xlnx-clock-wizard.c

   301	
   302	static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,
   303					       unsigned long parent_rate)
   304	{
   305		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   306		u32 reg, pre;
   307		u16 retries;
   308		int err;
   309		u64 vco_freq, rate_div, f, clockout0_div;
   310	
   311		err = clk_wzrd_get_divisors(hw, rate, parent_rate);
   312		if (err)
   313			pr_err("failed to get divisors\n");
   314	
   315		vco_freq = DIV_ROUND_CLOSEST((parent_rate * divider->valuem), divider->valued);
   316		rate_div = DIV_ROUND_CLOSEST((vco_freq * WZRD_FRAC_POINTS), rate);
   317	
   318		clockout0_div = rate_div / WZRD_FRAC_POINTS;
   319	
   320		pre = DIV_ROUND_CLOSEST((vco_freq * WZRD_FRAC_POINTS), rate);
   321		f = (u32)(pre - (clockout0_div * WZRD_FRAC_POINTS));
   322		f = f & WZRD_CLKOUT_FRAC_MASK;
   323	
 > 324		reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |
   325		      FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, f);
   326	
   327		writel(reg, divider->base + WZRD_CLK_CFG_REG(2));
   328		/* Set divisor and clear phase offset */
   329		reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->valuem) |
   330		      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->valued);
   331		writel(reg, divider->base + WZRD_CLK_CFG_REG(0));
   332		writel(divider->valueo, divider->base + WZRD_CLK_CFG_REG(2));
   333		writel(0, divider->base + WZRD_CLK_CFG_REG(3));
   334		/* Check status register */
   335		retries = WZRD_DR_NUM_RETRIES;
   336		while (retries--) {
   337			if (readl(divider->base + WZRD_DR_STATUS_REG_OFFSET) &
   338								WZRD_DR_LOCK_BIT_MASK)
   339				break;
   340		}
   341	
   342		if (!retries)
   343			return -ETIMEDOUT;
   344	
   345		/* Initiate reconfiguration */
   346		writel(WZRD_DR_BEGIN_DYNA_RECONF,
   347		       divider->base + WZRD_DR_INIT_REG_OFFSET);
   348	
   349		/* Check status register */
   350		retries = WZRD_DR_NUM_RETRIES;
   351		while (retries--) {
   352			if (readl(divider->base + WZRD_DR_STATUS_REG_OFFSET) &
   353								WZRD_DR_LOCK_BIT_MASK)
   354				break;
   355		}
   356	
   357		if (!retries)
   358			return -ETIMEDOUT;
   359	
   360		return 0;
   361	}
   362	
   363	static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,
   364					unsigned long parent_rate)
   365	{
   366		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   367		unsigned long flags = 0;
   368		int ret;
   369	
   370		if (divider->lock)
   371			spin_lock_irqsave(divider->lock, flags);
   372		else
   373			__acquire(divider->lock);
   374	
   375		ret = clk_wzrd_dynamic_all_nolock(hw, rate, parent_rate);
   376	
   377		if (divider->lock)
   378			spin_unlock_irqrestore(divider->lock, flags);
   379		else
   380			__release(divider->lock);
   381	
   382		return ret;
   383	}
   384	
   385	static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,
   386						      unsigned long parent_rate)
   387	{
   388		struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
   389		u32 m, d, o, div, reg, f;
   390	
   391		reg = readl(divider->base + WZRD_CLK_CFG_REG(0));
 > 392		d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
   393		m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg);
   394		reg = readl(divider->base + WZRD_CLK_CFG_REG(2));
   395		o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
   396		f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg);
   397	
   398		div = DIV_ROUND_CLOSEST(d * (WZRD_FRAC_POINTS * o + f), WZRD_FRAC_POINTS);
   399		return divider_recalc_rate(hw, parent_rate * m, div, divider->table,
   400				divider->flags, divider->width);
   401	}
   402	

---
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