[PATCH] clk: at91: sama7g5: fix parents of PDMCs' GCLK

[Nicolas Ferre]

On 07/03/2022 at 10:47, Claudiu Beznea - M18063 wrote:
> On 04.03.2022 20:26, Codrin Ciubotariu wrote:
>> Audio PLL can be used as parent by the GCLKs of PDMCs.
>>
>> Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
>> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu at microchip.com>
> 
> Reviewed-by: Claudiu Beznea <claudiu.beznea at microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre at microchip.com>
I'm taking this patch for a PR sent to Stephen for 5.18.

Best regards,
   Nicolas

>> ---
>>   drivers/clk/at91/sama7g5.c | 8 ++++----
>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
>> index e43458673afb..9a213ba9e58b 100644
>> --- a/drivers/clk/at91/sama7g5.c
>> +++ b/drivers/clk/at91/sama7g5.c
>> @@ -699,16 +699,16 @@ static const struct {
>>   	{ .n  = "pdmc0_gclk",
>>   	  .id = 68,
>>   	  .r = { .max = 50000000  },
>> -	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
>> -	  .pp_mux_table = { 5, 8, },
>> +	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
>> +	  .pp_mux_table = { 5, 9, },
>>   	  .pp_count = 2,
>>   	  .pp_chg_id = INT_MIN, },
>>   
>>   	{ .n  = "pdmc1_gclk",
>>   	  .id = 69,
>>   	  .r = { .max = 50000000, },
>> -	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
>> -	  .pp_mux_table = { 5, 8, },
>> +	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
>> +	  .pp_mux_table = { 5, 9, },
>>   	  .pp_count = 2,
>>   	  .pp_chg_id = INT_MIN, },
>>   
> 


-- 
Nicolas Ferre