[PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR

[Will Deacon]

On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> When a IAR register read races with a GIC interrupt RELEASE event,
> GIC-CPU interface could wrongly return a valid INTID to the CPU
> for an interrupt that is already released(non activated) instead of 0x3ff.
> 
> As a side effect, an interrupt handler could run twice, once with
> interrupt priority and then with idle priority.
> 
> [...]

Applied to arm64 (for-next/errata), thanks!

[1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
      https://git.kernel.org/arm64/c/24a147bcef8c

Cheers,
-- 
Will

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