[PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support

[Marc Zyngier]

On Sun, 27 Feb 2022 15:33:54 +0000,
Hector Martin <marcan at marcan.st> wrote:
> 
> On 25/02/2022 23.39, Marc Zyngier wrote:
> > On Thu, 24 Feb 2022 13:07:37 +0000,
> >>  		if (!(pending & irq_bit) &&
> >> -		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
> >> -			send |= AIC_IPI_SEND_CPU(cpu);
> >> +		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
> >> +			if (static_branch_likely(&use_fast_ipi))
> >> +				aic_ipi_send_fast(cpu);
> > 
> > OK, this is suffering from the same issue that GICv3 has, which is
> > that memory barriers don't provide order against sysregs. You need a
> > DSB for that, which is a pain. Something like this:
> 
> Doesn't the control flow here guarantee the ordering? atomic_read() must
> complete before the sysreg is written since there is a control flow
> dependency, and the prior atomic/barrier dance ensures that read is
> ordered properly with everything that comes before it.

Yes, you're right. Mixing memory ordering and control dependency hurts
my head badly, but hey, why not.

	M.

-- 
Without deviation from the norm, progress is not possible.