[PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
kernel test robot
lkp at intel.com
Mon Jun 27 18:28:58 PDT 2022
Hi Sricharan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linusw-pinctrl/devel linus/master v5.19-rc4 next-20220627]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Sricharan-R/Add-minimal-boot-support-for-IPQ5018/20220622-001751
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20220628/202206280917.m3YJRqsF-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 016342e319fd31e41cf5ed16a6140a8ea2de74dd)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/d7a0e1d14ecebd407df120468035592246a71cd6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sricharan-R/Add-minimal-boot-support-for-IPQ5018/20220622-001751
git checkout d7a0e1d14ecebd407df120468035592246a71cd6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/kernel/ drivers/clk/qcom/ drivers/pinctrl/qcom/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/qcom/gcc-ipq5018.c:118:37: warning: unused variable 'gcc_xo_gpll0_out_main_div2' [-Wunused-const-variable]
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
^
>> drivers/clk/qcom/gcc-ipq5018.c:123:32: warning: unused variable 'gcc_xo_gpll0_out_main_div2_map' [-Wunused-const-variable]
static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
^
>> drivers/clk/qcom/gcc-ipq5018.c:201:37: warning: unused variable 'gcc_xo_gpll0_gpll4_gpll2' [-Wunused-const-variable]
static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll2[] = {
^
>> drivers/clk/qcom/gcc-ipq5018.c:208:32: warning: unused variable 'gcc_xo_gpll0_gpll4_gpll2_map' [-Wunused-const-variable]
static const struct parent_map gcc_xo_gpll0_gpll4_gpll2_map[] = {
^
4 warnings generated.
vim +/gcc_xo_gpll0_out_main_div2 +118 drivers/clk/qcom/gcc-ipq5018.c
117
> 118 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
119 { .fw_name = "xo", .name = "xo", },
120 { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", },
121 };
122
> 123 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
124 { P_XO, 0 },
125 { P_GPLL0_DIV2, 1 },
126 };
127
128 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
129 { .fw_name = "xo", .name = "xo", },
130 { .fw_name = "gpll0", .name = "gpll0", },
131 { .fw_name = "gpll4", .name = "gpll4", },
132 };
133
134 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
135 { P_XO, 0 },
136 { P_GPLL0, 1 },
137 { P_GPLL4, 2 },
138 };
139
140 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
141 { .fw_name = "xo", .name = "xo", },
142 { .fw_name = "gpll0", .name = "gpll0", },
143 { .fw_name = "sleep_clk", .name = "sleep_clk", },
144 };
145
146 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
147 { P_XO, 0 },
148 { P_GPLL0, 2 },
149 { P_CORE_PI_SLEEP_CLK, 6 },
150 };
151
152 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
153 { .fw_name = "xo", .name = "xo", },
154 { .fw_name = "gpll0", .name = "gpll0", },
155 { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", },
156 { .fw_name = "sleep_clk", .name = "sleep_clk", },
157 };
158
159 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
160 { P_XO, 0 },
161 { P_GPLL0, 1 },
162 { P_GPLL0_DIV2, 4 },
163 { P_CORE_PI_SLEEP_CLK, 6 },
164 };
165
166 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
167 { .fw_name = "xo", .name = "xo", },
168 { .fw_name = "gpll0", .name = "gpll0", },
169 { .fw_name = "gpll2", .name = "gpll2", },
170 { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", },
171 };
172
173 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
174 { P_XO, 0 },
175 { P_GPLL0, 1 },
176 { P_GPLL2, 2 },
177 { P_GPLL0_DIV2, 4 },
178 };
179
180 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
181 { .fw_name = "xo", .name = "xo", },
182 { .fw_name = "gpll4", .name = "gpll4", },
183 { .fw_name = "gpll0", .name = "gpll0", },
184 { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", },
185 };
186
187 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
188 { P_XO, 0 },
189 { P_GPLL4, 1 },
190 { P_GPLL0, 2 },
191 { P_GPLL0_DIV2, 4 },
192 };
193
194 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
195 { P_XO, 0 },
196 { P_GPLL4, 1 },
197 { P_GPLL0, 3 },
198 { P_GPLL0_DIV2, 4 },
199 };
200
> 201 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll2[] = {
202 { .fw_name = "xo", .name = "xo", },
203 { .fw_name = "gpll0", .name = "gpll0", },
204 { .fw_name = "gpll4", .name = "gpll4", },
205 { .fw_name = "gpll2", .name = "gpll2", },
206 };
207
> 208 static const struct parent_map gcc_xo_gpll0_gpll4_gpll2_map[] = {
209 { P_XO, 0 },
210 { P_GPLL0, 1 },
211 { P_GPLL4, 3 },
212 { P_GPLL2, 4 },
213 };
214
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