On 2022-06-15 17:12, yf.wang--- via iommu wrote:
> From: Yunfei Wang <yf.wang at mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
> pgtable support at most 35bit PA.
I'm not sure how this works in practice, given that you don't seem to be
setting the IOMMU's own DMA masks to more than 32 bits, so the DMA
mapping in io-pgtable is going to fail if you ever do actually allocate
a pagetable page above 4GB :/
> Signed-off-by: Ning Li <ning.li at mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang at mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 3d62399e8865..4dbc33758711 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -138,6 +138,7 @@
> /* PM and clock always on. e.g. infra iommu */
> #define PM_CLK_AO BIT(15)
> #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
> +#define PGTABLE_PA_35_EN BIT(17)
>
> #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
> ((((pdata)->flags) & (mask)) == (_x))
> @@ -240,6 +241,7 @@ struct mtk_iommu_data {
> struct mtk_iommu_domain {
> struct io_pgtable_cfg cfg;
> struct io_pgtable_ops *iop;
> + u32 ttbr;
>
> struct mtk_iommu_bank_data *bank;
> struct iommu_domain domain;
> @@ -596,6 +598,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
> .iommu_dev = data->dev,
> };
>
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
> +
> if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
> dom->cfg.oas = data->enable_4GB ? 33 : 32;
> else
> @@ -684,8 +689,8 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
> goto err_unlock;
> }
> bank->m4u_dom = dom;
> - writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - bank->base + REG_MMU_PT_BASE_ADDR);
> + bank->m4u_dom->ttbr = MTK_IOMMU_ADDR(dom->cfg.arm_v7s_cfg.ttbr);
> + writel(bank->m4u_dom->ttbr, data->base + REG_MMU_PT_BASE_ADDR);
To add to my comment on patch #1, having to make this change here
further indicates that you're using it the wrong way.
Thanks,
Robin.
>
> pm_runtime_put(m4udev);
> }
> @@ -1366,8 +1371,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
> writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
> writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
> writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
> - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - base + REG_MMU_PT_BASE_ADDR);
> + writel(m4u_dom->ttbr, base + REG_MMU_PT_BASE_ADDR);
> } while (++i < data->plat_data->banks_num);
>
> /*
> @@ -1401,7 +1405,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> static const struct mtk_iommu_plat_data mt6779_data = {
> .m4u_plat = M4U_MT6779,
> .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
> - MTK_IOMMU_TYPE_MM,
> + MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .banks_num = 1,
> .banks_enable = {true},